Forming dual gate oxide thickness on vertical transistors by...

Details Forming dual gate oxide thickness on vertical transistors by... Forming dual gate oxide thickness on vertical transistors by...

2002-06-04

2003-08-26

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06610575

ABSTRACT:

BACKGROUND OF THE INVENTION
One way to increase chip packing density is to make vertical transistors. However, vertical transistor fabrication elevates the complexity of the process steps and conditions. This complexity is magnified when vertical transistors are fabricated with different gate oxide thicknesses for higher levels of circuitry integration which makes the task even more challenging and demanding.
U.S. Pat. No. 5,757,038 to Tiwari et al. describes a self-aligned dual gate MOSFET with an ultra-narrow channel.
U.S. Pat. Nos. 6,013,548 and 6,077,745 each to Burns, Jr. et al. both describe a method of fabricating self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array.
U.S. Pat. No. 5,324,673 to Fitch et al. describes a method of fabricating vertical transistors
U.S. Pat. No. 6,030,871 to Eitan describes a method of manufacturing two bit ROM cell using an angled implant.
U.S. Pat. No. 6,080,682 to Ibok describes a methodology for achieving dual gate oxide thicknesses.
U.S. Pat. No. 6,150,670 to Faltermeier et al. describes a process for fabricating a uniform gate oxide of a vertical transistor.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of fabricating vertical transistors having different gate oxide thicknesses.
Another object of one or more embodiments of the present invention to provide an improved method of fabricating vertical transistors having different gate oxide thicknesses by the use of selective ion implantation.
A further object of one or more embodiments of the present invention to provide an improved method of fabricating vertical transistors having different gate oxide thicknesses by the use of selective plasma doping.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked. Gate oxide is grown on the outer side walls and the inner side walls of the first and second pillars wherein the gate oxide grown upon the modified surfaces of the at least one of the doped outer or inner side walls is thicker than the gate oxide grown upon the nonmodified surfaces of the at least one of the non-doped outer or inner side walls.


REFERENCES:
patent: 5324673 (1994-06-01), Fitch et al.
patent: 5757038 (1998-05-01), Tiwari et al.
patent: 6013548 (2000-01-01), Burns, Jr. et al.
patent: 6030871 (2000-02-01), Eitan
patent: 6077745 (2000-06-01), Burns, Jr. et al.
patent: 6080682 (2000-06-01), Ibok
patent: 6150670 (2000-11-01), Faltermeier et al.
patent: 6258673 (2001-07-01), Houlihan et al.
patent: 6440801 (2002-08-01), Furukawa et al.
patent: 2002/0102827 (2002-08-01), Chen

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