Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-31
2001-02-13
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06187626
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for forming a capacitor structure in an inter-polysilicon dielectric, more particularly for forming a semi-recessed capacitor structure in an inter-polysilicon dielectric.
2. Description of the Prior Art
In the prior art, first of all, as
FIG. 1A
, an inter-polysilicon dielectric layer
11
is deposited onto the surface of a semiconductor substrate
120
. Especially, there is a cell
150
formed into the semiconductor substrate
120
already.
Consequentially, as
FIG. 1B
, a portion of the inter-polysilicon dielectric layer
11
is etched as an opening
180
by using the conventional dry etching. This opening
180
is a trapezoid-like structure, especially it owns the narrow lower and the wide upper structure.
Then, as
FIG. 1C
, the polysilicon layer
12
is deposited over the surface of the inter-polysilicon dielectric
11
and fills up the opening
180
.
As the
FIG. 1D
, the portion of the polysilicon layer
12
is etched using the conventional dry etching to form a bottom plate of the capacitor. Here, the photoresist layer
162
is used as an etch mask. If the thin silicon nitride layer is formed on the surface of the polysilicon, the topographic effect of the silicon nitride layer will be produced, such as legend
170
.
In the incubation time of the process, the thickness of nitride deposited on the oxide is thinner than the nitride deposited on the silicon. While the thickness of oxide-nitride-oxide layer is reduce, the topographic effect of the thin nitride deposition in the process will make the nitride thickness between the silicon and inter-polysilicon dielectric boundary becomes too thin, also this withstands the following wet oxidation process. At this time, grain boundary oxidation may occur at the neck of polysilicon via, which results in abnormal increment of node contact resistance.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a capacitor structure that substantially improves the topographic effect from the silicon nitride layer.
In the preferred embodiment, the silicon nitride layer located on the polysilicon dielectric layer and etching back a portion of the polysilicon layer can form the bottom plate of capacitor.
In the preferred embodiment, the thickness of silicon nitride layer can be reduced when the polysilicon layer is etching back.
In one embodiment, first of all, a first oxide layer is formed onto the surface of a semiconductor substrate. A first nitride layer is formed onto the surface of the first oxide layer. Then, a second oxide layer is formed onto the surface of the second nitride layer. Again, a second nitride layer is formed onto the surface of the second nitride layer. Next, a third oxide layer is formed onto the surface of the second nitride layer. Then, a first photoresist is formed onto the first nitride layer to define a first opening of a polysilicon via.
A portion of the third oxide layer, a portion of the second nitride layer, a portion of the second oxide layer and a portion of the first nitride layer are all etched using the first photoresist layer as an etch mask until the semiconductor substrate is exposed to form a first opening of the polysilicon via, that is a trapezoid-like opening having a wide upper and a narrow lower. The first photoresist is removed. A first polysilicon layer is formed on the surface of the semiconductor substrate and over the surface of the third oxide layer, wherein the first polysilicon layer fills up the first opening. Then, a portion of the first polysilicon layer is etched until the third oxide layer is exposed, whereby the surface of the first polysilicon layer is lower than the surface of the third oxide layer. A dielectric layer is formed over the surface of the polysilicon layer and the third oxide layer.
Next, a second photoresist layer is formed over the surface of the dielectric layer to define a capacitor region. Then, a portion of the dielectric layer, a portion of the third oxide layer, of the second nitride layer and some of the second oxide layer are etched until the rest of the second oxide layer is still remained. The second photoresist is removed. Then, a second polysilicon layer is deposited over the dielectric layer. Next, a portion of the second polysilicon layer is etched back using the first dielectric layer as a stop layer so that the surface of the second polysilicon layer is lower than the surface of the dielectric layer.
Finally, the dielectric layer and the third oxide layer are etched using the third oxide layer as a stop layer until the surface of the second nitride layer is exposed. Thus, the second polysilicon layer is remained into the second nitride layer and the second oxide layer, whereby completing the capacitor structure having the semi-recessed structure.
REFERENCES:
patent: 6103568 (2000-08-01), Fijiwara
patent: 6103586 (2000-08-01), Chetlur et al.
Harness & Dickey & Pierce P.L.C.
Tsai Jey
United Microelectronics Corp.
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