Forming a conductive structure in a semiconductor device

Details Forming a conductive structure in a semiconductor device Forming a conductive structure in a semiconductor device

2000-07-20

2003-07-22

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S769000, C438S787000

Reexamination Certificate

active

06596595

ABSTRACT:

BACKGROUND
The invention relates to forming a conductive structure in a semiconductor device.
Advanced integrated circuits in a semiconductor device require high speed interconnecting lines between circuits for improved device speed. Interconnecting lines are typically made of metal, e.g., aluminum, titanium. However, in some parts of a semiconductor device, particularly in regions where components are densely packed (such as the array of a memory device), or in regions where further heat steps are needed after formation of the interconnecting line during the manufacturing process, other materials are also widely used to form interconnecting lines, e.g., doped polysilicon or N+ or P+ diffused regions.
The different types of interconnecting lines exhibit different resistivities, with metal generally having the lowest resistivity. Polysilicon, which is also typically used as the conductive electrode at the gate of an N-channel or P-channel metal-oxide-silicon field effect transistor (MOSFET), exhibits a higher resistivity than metal.
As the speed requirements of semiconductors increase, the resistance of interconnecting lines, especially those formed of a higher resistivity material (such as polysilicon) reduces switching speeds of circuits in the device. The resistance of a line increases proportionately with its length. Thus, a polysilicon line running over a long length and connected to a large capacitive load, such as a wordline in a memory array connected to multiple transistors in the array, would cause a high RC delay during circuit switching.
One approach to reduce the resistivity of a polysilicon interconnect line is to use a polycide structure, in which a low resistance silicide (e.g., WSix) is formed on top of a doped polysilicon layer. This effectively forms a two-layer interconnect line in which the silicide layer provides a low resistivity conductive path.
Three-layer interconnecting lines have also been proposed, including a polymetal composite structure having tungsten (W) as the top layer, tungsten silicide nitride (WSiN) as the intermediate layer, and polysilicon as the bottom layer. The polymetal structure has a resistivity lower than the polycide structure that includes tungsten silicide on polysilicon.
SUMMARY
In general, according to one embodiment, a method of forming a conductive structure in a semiconductor device includes forming a lower electrically conductive layer on a support surface and forming an electrically conductive barrier over the lower layer. Further, an upper conductive layer is formed over the barrier layer, the upper conductive layer including metal silicide.
Other features and embodiments will become apparent from the following description and from the claims.


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