Forming a capacitor structure of a semiconductor

Details Forming a capacitor structure of a semiconductor Forming a capacitor structure of a semiconductor

2000-01-31

2001-02-20

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S240000, C438S250000, C438S381000, C438S393000

Reexamination Certificate

active

06190956

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to form a capacitor structure of a semiconductor, more particularly the method is completed by improving the thickness of the silicon nitride layer.
2. Description of the Prior Art
In the prior art, first of all, as
FIG. 1A
, an atmosphere-pressure oxide layer
121
is deposited onto the surface of a semiconductor substrate
120
. Especially, there are cells
150
formed into the semiconductor substrate
120
already. Then, a silicon nitride
122
is formed on the surface of the atmosphere-pressure oxide layer
121
. Again, a low-pressure oxide layer
123
is formed on the surface of the silicon nitride
122
. Then, a first photoresist
161
is formed onto the first nitride layer
123
to define a polysilion dielectric layer
181
.
Consequentially, as
FIG. 1B
, a portion of the low-pressure oxide layer
123
, the nitride layer
122
and a portion of the atmosphere-pressure oxide layer
121
are all etched as columns using the conventional dry etching to form an opening
181
. These columns will conclude the low-pressure oxide layer
123
, the nitride layer
122
and the atmosphere-pressure oxide layer
121
.
Then, as
FIG. 1C
, by the chemical vapor deposition, the first polysilicon layer
124
is formed on the surface of the low-pressure oxide layer
123
and is filled up into the first opening
180
and is covered on the low-pressure oxide layer
123
. The second photoresist
162
is formed on the polysilicon layer
124
to define the opening of the polysilicon via.
As the
FIG. 1D
, the portion of the first polysilicon layer
124
is etched using the dry etching to form a bottom plate of the capacitor. Here, the photoresist layer
162
is used as an etch mask.
Next, as
FIG. 1E
, a silicon nitride layer
125
is formed on the surface of the polysilicon layer
124
using the chemical vapor deposition. The thickness of this silicon nitride layer
125
is about 50 angstroms. There is the topographic effect happened on the silicon nitride layer
125
, such as legend
10
. This topographic effect will seriously damage the function of cell.
As
FIG. 1F
, the wet oxidation layer
126
is deposited onto the silicon nitride
125
using the wet chemical deposition to form the top plate
127
of the capacitor. Therefore the capacitor structure is completed.
In the incubation time of the process, the thickness of nitride deposited on the oxide is thinner than the nitride deposited on the silicon. While the thickness of oxide-nitride-oxide layer is reduce, the topographic effect of the thin nitride deposition in the process will make the nitride thickness between the silicon and inter-polysilicon dielectric boundary becomes too thin, also this withstands the following wet oxidation process. At this time, grain boundary oxidation may occur at the neck of polysilicon via, which results in abnormal increment of node contact resistance.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a capacitor structure that substantially improves the topographic effect from the silicon nitride layer.
In the preferred embodiment, the silicon nitride layer located on the polysilicon dielectric layer and etching back a portion of the polysilicon layer can form the bottom plate of capacitor.
In the preferred embodiment, the thickness of silicon nitride layer can be reduced when the polysilicon layer is etching back.
In one embodiment, first of all, a first oxide layer is deposited onto the surface of a semiconductor substrate. A first nitride layer is formed onto the surface of the first nitride layer. Then, a first photoresist is formed onto the first nitride layer to define a first opening.
Consequentially, a portion of the first nitride layer and a portion of the first oxide layer are all etched using the first photoresist layer as an etch mask until the semiconductor substrate being exposed to define a first opening. Then, the first polysilicon layer is formed on the surface of the semiconductor substrate and on the surface of the first nitride layer, wherein the first polysilicon layer is filled up into the first opening and is covered on said first nitride layer. The portion of the first polysilicon layer is reduced to a specified thickness for the surface of the first polysilicon layer until the remained first polysilicon layer can cover the first nitride layer and covering the first opening. Next, boron phosphorus silicon glass layer blankly and conformably is formed on the surface of the first polysilicon layer. A second photoresist is formed on the boron phosphorus silicon glass layer to define a capacitor region. Then, a portion of said boron phosphorus silicon glass layer is etched until the first polysilicon layer is exposed to form a second opening on the first opening.
A second polysilicon layer is deposited into the second opening to cover the surface of the boron phosphorus silicon glass layer. Next, a portion of the second polysilicon layer is etched back until the surface of the boron phosphorus silicon glass layer is exposed. Next, the boron phosphorus silicon glass layer is etched, whereby the second polysilicon layer is remained on the surface of the first polysilicon. Then, the first polysilicon layer is etched back until the first nitride layer is exposed, wherein the first polysilicon layer is used as a bottom plate of the capacitor.
A second nitride layer is formed onto the surface of the first nitride layer, the surface of the first polysilicon layer and the surface of the second polysilicon layer. Next, a second oxide layer is deposited onto the surface of the second nitride layer. Finally, a conductive layer is formed as a top plate of capacitor, whereby a capacitor structure is completed and there are a top plate and a bottom plate.


REFERENCES:
patent: 5710073 (1998-01-01), Jeng et al.
patent: 6066528 (2000-05-01), Fazan et al.
patent: 6097051 (2000-08-01), Torri et al.

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