Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-03-11
2008-08-26
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S648000, C438S672000, C257SE21295, C257SE21508
Reexamination Certificate
active
07416980
ABSTRACT:
Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.
REFERENCES:
patent: 6297146 (2001-10-01), Lopatin
patent: 6383923 (2002-05-01), Brown et al.
patent: 6861349 (2005-03-01), Lopatin et al.
patent: 2006/0071340 (2006-04-01), Dubin et al.
Dubin Valery
Fang Ming
Zhong Ting
Geyer Scott B.
Intel Corporation
Intel Corporation
Lee Cheung
Ortiz Kathy J.
LandOfFree
Forming a barrier layer in interconnect joints and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Forming a barrier layer in interconnect joints and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Forming a barrier layer in interconnect joints and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4019360