Formation of ultra-shallow depth source/drain extensions for...

Details Formation of ultra-shallow depth source/drain extensions for... Formation of ultra-shallow depth source/drain extensions for...

2002-10-18

2004-04-27

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S232000, C438S301000, C438S305000

Reexamination Certificate

active

06727136

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the manufacture of high speed MOS semiconductor devices with improved transistor performance, and to MOS transistor devices obtained thereby. Specifically, the present invention relates to a method for fabricating MOS transistors with ultra-shallow depth source/drain extensions for providing improved device performance characteristics, which method utilizes strained lattice semiconductor substrates.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of 0.18 &mgr;m and below, e.g., such as 0.15 &mgr;m and 0.12 &mgr;m, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor materials and manufacturing techniques.
A problem associated with reduction of transistor design features to 0.18 &mgr;m and below is the difficulty in forming ultra-shallow source/drain extension regions in conventional silicon (Si)-wafer based substrate materials. Specifically, ultra-shallow depth source/drain extensions having sufficiently low series resistance, thus high doping levels, are required for obtaining high quality transistor performance characteristics, including, inter alia, I
off
vs. I
on
and saturation threshold roll-off voltage V
ts
. This problem is especially severe in the manufacture of p-channel MOS transistors comprising a boron (B)-containing p-type dopant species, largely due to the ease with which the small-sized boron atoms/ions diffuse in conventional Si-based semiconductor substrates.
As a consequence of the above-described and other shortcomings and drawbacks of conventional Si-based semiconductor substrates when utilized in the manufacture of ULSI semiconductor devices with design features below about 0.18 &mgr;m, there recently has been much interest in various approaches with the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed “strained silicon”.
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer (sometimes referred to as a “cap” layer) is epitaxially grown on a relaxed, graded composition Si—Ge buffer layer, which Si—Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when epitaxially deposited on the Si—Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Si—Ge) comprised of atoms which are spaced further apart, they “stretch” to align with the underlying Si and Ge atoms, thereby “stretching” or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron mobility/current flow in strained Si may be up to about 70% higher compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
In view of the above, there exists a need for improved methodology for fabrication of high speed, sub-micron-dimensioned MOS transistors and CMOS devices which facilitates obtainment of the transistor performance advantages accruing from low series resistance, ultra-shallow depth source/drain extension regions not obtainable with conventional Si-based substrate materials, i.e., improved I
off
vs. I
on
and V
ts
, and the enhanced device speeds attributable to the use of strained lattice semiconductor substrates.
The present invention, wherein high performance MOS transistors and CMOS devices comprising low series resistance, ultra-shallow depth source/drain extension regions, are formed in strained lattice semiconductor substrates by a process wherein the source/drain extension region depth is limited by the thickness of the “cap” layer, effectively overcomes problems associated with the manufacture of MOS transistors with ultra-shallow depth source/drain extension regions in conventional Si-based semiconductor substrates. As a consequence, the inventive methodology facilitates manufacture of high speed, high performance, reduced power consumption semiconductor devices utilizing strained semiconductor technology. Further the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various semiconductor devices and/or components therefor which require ultra-shallow junction depths and low series resistance for optimal performance.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for manufacturing a semiconductor device.
Another advantage of the present invention is an improved method of manufacturing a MOS transistor device with ultra-shallow depth source/drain extension regions.
Still another advantage of the present invention is an improved method of manufacturing a MOS transistor comprising a strained lattice semiconductor layer.
A further advantage of the present invention is an improved semiconductor device.
A still further advantage of the present invention is an improved MOS transistor having ultra-shallow depth source/drain regions.
A yet further advantage of the present invention is an improved MOS transistor comprising a strained lattice semiconductor layer.
Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising sequential steps of:
(a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and
(b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of said underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.
According to embodiments of the present invention, step (a) comprises providing a semiconductor substrate which further comprises a layer of a third semiconductor material beneath the layer of a second semiconductor material.
In accordance with preferred embodiments of the invention, the device comprises at least one MOS transistor, and step (a) comprises providing a MOS transistor precursor structure including a semiconductor substrate with at least one gate oxide/gate electrode layer stack on at l

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