Formation of STI (shallow trench isolation) structures...

Details Formation of STI (shallow trench isolation) structures... Formation of STI (shallow trench isolation) structures...

2001-10-01

2003-01-21

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S257000, C438S424000, C438S435000, C438S436000, C438S437000

Reexamination Certificate

active

06509232

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to flash memory devices, and more particularly, to a method for forming STI (shallow trench isolation) structures within the core and periphery areas of a flash memory device with rounding at corners of the semiconductor substrate adjacent the STI structures and with preservation of the integrity of the tunnel dielectric of the core flash memory cells.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a flash memory cell
100
of a flash memory device includes a tunnel dielectric
102
typically comprised of silicon dioxide (SiO
2
) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric
102
is disposed on a core active device area
103
of a semiconductor substrate or a p-well. In addition, a floating gate
104
, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric
102
. A floating dielectric
106
, typically comprised of silicon dioxide (SiO
2
) or ONO (a sandwich of oxide-nitride-oxide, as known to one of ordinary skill in the art of integrated circuit fabrication), is disposed over the floating gate
104
. A control gate
108
, comprised of a conductive material such as polysilicon, is disposed over the floating dielectric
106
.
A drain bit line junction
110
that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within the core active device area
103
of the semiconductor substrate or p-well toward a left sidewall of the floating gate
104
in
FIG. 1. A
source bit line junction
114
that is doped with the junction dopant is formed within the core active device area
103
of the semiconductor substrate or p-well
106
toward a right sidewall of the floating gate
104
of FIG.
1
. The core active device area
103
is defined by surrounding STI (shallow trench isolation) structures
109
comprised of an insulating material such as silicon dioxide (SiO
2
) for example. Such a flash memory cell
100
comprising a flash memory device is known to one of ordinary skill in the art of integrated circuit fabrication.
During the program or erase operations of the flash memory cell
100
of
FIG. 1
, charge carriers are injected into or injected out of the floating gate
104
. Such variation of the amount of charge carriers within the floating gate
104
alters the threshold voltage of the flash memory cell
100
, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate
104
, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the floating gate
104
, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell
100
for example, a voltage of +9 Volts is applied on the control gate
108
, a voltage of +5 Volts is applied on the drain bit line junction
110
, and a voltage of 0 Volts is applied on the source bit line junction
114
and on the semiconductor substrate or p-well
103
. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are injected into the floating gate
104
to increase the threshold voltage of the flash memory cell
100
during programming of the flash memory cell
100
.
Alternatively, during erasing of the flash memory cell
100
, a voltage of −9.5 Volts is applied on the control gate
108
, a voltage of 0 Volts is applied on the drain bit line junction
110
, and a voltage of +4.5 Volts is applied on the source bit line junction
114
and on the semiconductor substrate or p-well
103
for example. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are pulled out of the floating gate
104
to decrease the threshold voltage of the flash memory cell
100
during erasing of the flash memory cell
100
. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of flash memory technology.
In an alternative channel erase process, a voltage of −9.5 Volts is applied on the control gate
108
and a voltage of +9 Volts is applied on the semiconductor substrate or p-well
103
with the drain and source bit line junctions
110
and
114
floating. With such bias, when the flash memory cell
100
is an N-channel flash memory cell, electrons are pulled out of the floating gate
104
to the substrate or p-well
103
to decrease the threshold voltage of the flash memory cell
100
during erasing of the flash memory cell
100
.
FIG. 2
illustrates an example semiconductor die
150
having a flash memory device fabricated thereon. The flash memory device includes a core area
152
having an array of flash memory cells fabricated thereon and a periphery area
154
having logic circuitry fabricated thereon, as known to one of ordinary skill in the art of flash memory devices.
FIG. 3
illustrates the array of flash memory cells fabricated in the core area
152
, as known to one of ordinary skill in the art of flash memory technology. Referring to
FIG. 3
, the array of flash memory cells
200
includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell
100
of FIG.
1
. The array of flash memory cells
200
of
FIG. 3
is illustrated with 2 columns and 2 rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells such as 512 rows and 512 columns of flash memory cells for example.
Further referring to
FIG. 3
, in the array of flash memory cells
200
, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In
FIG. 3
, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line
202
, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line
204
. In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In
FIG. 3
, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line
206
, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line
208
. Further referring to
FIG. 3
, the source terminal of all flash memory cells of the array
200
are coupled together to a source voltage V
SS
, and the substrate or p-well terminal of all flash memory cells of the array
200
are coupled together to a substrate voltage V
SUB
.
Referring to
FIGS. 2 and 4
, the logic circuitry of the periphery area
154
is comprised of conventional MOSFETs (metal oxide semiconductor field effect transistor)
250
. The conventional MOSFET
250
includes a gate dielectric
252
typically comprised of silicon dioxide (SiO
2
) formed over a periphery active device area
254
of a semiconductor substrate or a p-well. In addition, a gate structure
256
, comprised of a conductive material such as polysilicon, is disposed over the gate dielectric
252
.
A drain junction
258
that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within the active device area
254
of the semiconductor substrate or p-well toward a left sidewall of the gate structure
256
. A source junction
260
that is doped with the junction dopant is formed within the active device area
254
of the semiconductor substrate or p-well toward a right sidewall of the gate structure
256
. The periphery active device area
254
is

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