Formation of self-aligned vertical connector

Details Formation of self-aligned vertical connector Formation of self-aligned vertical connector

2002-10-25

2003-10-28

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S243000, C438S386000, C438S387000, C438S389000, C438S392000, C438S249000, C257S301000

Reexamination Certificate

active

06638815

ABSTRACT:

TECHNICAL FIELD
The field of the invention is that of forming three-dimensional structures in integrated circuit processing, in particular DRAM cells or other structures that use vertical transistors.
BACKGROUND OF THE INVENTION
Several novel DRAMs use cells with vertical transistors in order to reduce space by stacking the transistor generally above the capacitor and to avoid problems with scaling the pass transistor.
In addition, circuit configurations have been proposed that involve placing two or more vertical transistors above one another. In that case also, the current path from one transistor to another must extend transversely outside the trench and into the semiconductor substrate.
Since the trench capacitor center electrode (or a lower interconnect electrode) is located in the trench that also holds the transistor gate, the current path through the transistor body must extend transversely outside the trench and into the semiconductor substrate.
In the case of stacked capacitor cells with buried bitlines or in the case of buried wiring levels below vertical transistors, the current path must similarly extend transversely outside the trench carrying the buried bitline or wiring level.
Prior art methods of introducing dopants into the substrate have involved outdiffusing from a heavily doped layer of poly (the inner electrode) and heating the wafer to drive the dopant into the substrate. As dimensions shrink, the inevitable manufacturing process fluctuations result in a greater percentage variation in vertical height between the capacitor and the transistor. At the same time, reduction in ground rules requires closer lateral spacing between cells and prevents the use of an increased dopant outdiffusion to provide a reliable current path.
The process of etching the pad oxide produces a “divot” where the oxide is undercut. This can give rise to difficulties in later processing.
SUMMARY OF THE INVENTION
The invention relates to a method of making a three-dimensional electrical structure making contact between two circuit elements that are separated vertically and horizontally.
A feature of the invention is the diffusion of dopant from an aperture cut into a semiconductor substrate, thereby extending a conductive path laterally into the substrate.
Another feature of the invention is the opening of a diffusion window in the sidewall of a trench for entry of dopant to form a self-aligned conductive path.
Another feature of the invention is the use of a temporary layer to provide an offset for a hardmask formed on the interior of a trench.
Yet another feature of the invention is that the pad oxide is not attacked during the wet etch of the collar.
Yet another feature of the invention is that there is only one Trench Top Oxide (TTO) layer required.
Yet another feature of the invention is an additional recess step to expose the side of an oxide collar for a novel strap formation technique.
Yet another feature of the invention is the use of a temporary layer to define a diffusion window for diffusion of dopant into the substrate to form a self-aligned extension of the buried strap in a DRAM cell having a vertical transistor.


REFERENCES:
patent: 6040213 (2000-03-01), Canale et al.
patent: 6204527 (2001-03-01), Sudo et al.
patent: 6410391 (2002-06-01), Zelsacher
patent: 6440793 (2002-08-01), Divakaruni et al.
patent: 2001/0038113 (2001-11-01), Bronner et al.
patent: 2002/0005538 (2002-01-01), Luetzen et al.
patent: 2003/0013259 (2003-01-01), Chidambarrao et al.
patent: 2003/0022457 (2003-01-01), Gutsche et al.
patent: 05067749 (1993-03-01), None

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