Formation of self-aligned passivation for interconnect to...

Details Formation of self-aligned passivation for interconnect to... Formation of self-aligned passivation for interconnect to...

2000-08-03

2001-10-30

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S629000, C438S633000, C438S637000, C438S640000, C438S643000, C438S648000, C438S660000, C438S687000

Reexamination Certificate

active

06309959

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of interconnects within integrated circuits, and more particularly, to formation of a self-aligned passivation material at the top surface of the interconnect, such as copper interconnect for example, to effectively encapsulate the interconnect for preventing material comprising the interconnect from drifting into surrounding insulating material.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to
FIG. 1
, a cross sectional view is shown of a copper interconnect
102
within a trench
104
formed in an insulating layer
106
. The copper interconnect
102
within the insulating layer
106
is formed on a semiconductor wafer
108
such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect
102
is typically formed by etching the trench
104
as an opening within the insulating layer
106
, and the trench
104
is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to
FIG. 1
, the insulating layer
106
may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. Copper may easily diffuse into such an insulating layer
106
, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material
110
is deposited to surround the copper interconnect
102
within the insulating layer
106
on the sidewalls and the bottom wall of the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material
110
is disposed between the copper interconnect
102
and the insulating layer
106
for preventing diffusion of copper from the copper interconnect
102
to the insulating layer
106
to preserve the integrity of the insulating layer
106
.
Further referring to
FIG. 1
, an encapsulating layer
112
is deposited as a passivation layer to encapsulate the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer
112
is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect
102
does not easily diffuse into such a dielectric of the encapsulating layer
112
.
Referring to
FIG. 1
, in the prior art, the encapsulating layer
112
of silicon nitride is deposited directly onto an exposed surface of the copper interconnect
102
and the surrounding insulating layer
106
after the exposed surface of the copper interconnect
102
and the surrounding insulating layer
106
are polished to a level surface. Unfortunately, the silicon nitride of the encapsulating layer
112
does not bond well to the copper at the exposed surface of the copper interconnect
102
.
Thus, although copper does not diffuse easily through the encapsulating layer
112
of silicon nitride, copper from the copper interconnect
102
laterally drifts from the interface between the copper interconnect
102
and the encapsulating layer
112
of silicon nitride along the bottom surface
114
of the encapsulating layer
112
of silicon nitride because of the weak bonding of the copper interconnect
102
and the encapsulating layer
112
of silicon nitride.
The copper that laterally drifts from the interface between the copper interconnect
102
and the encapsulating layer
112
of silicon nitride along the bottom surface
114
of the encapsulating layer
112
eventually diffuses into the insulating layer
106
to disadvantageously degrade the insulating property of the insulating layer
106
and to possibly degrade the copper interconnect electromigration life-time. Nevertheless, use of copper metallization is desirable for further scaling down integrated circuit dimensions because of the lower bulk resistivity and the higher electromigration tolerance. Thus, a mechanism is desired for preventing the drift of copper from the copper interconnect
102
into the insulating layer
106
.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, an additional passivation material that is more reliable than just a bulk passivation layer is formed to be self-aligned at the top surface of the interconnect, such as copper interconnect for example, to effectively encapsulate the interconnect for preventing material comprising the interconnect from drifting into surrounding insulating material.
In one aspect of the present invention, an interconnect opening of an integrated circuit is filled with a conductive fill with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first conductive material is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The interconnect opening is further filled with a second conductive material by growing the second conductive material from the seed layer, to form a conductive fill of the first conductive material and the second conductive material within the interconnect opening.
The first conductive material and the second conductive material are comprised of a bulk metal, and at least one of the first conductive material and the second conductive material is a metal alloy having an alloy dopant in the bulk metal. The first conductive material and the second conductive material are polished away from the insulating layer surrounding the interconnect opening such that the conductive fill is contained within the interconnect opening. In addition, a plasma treatment process is performed by placing the semiconductor wafer within a plasma reaction chamber with a reducing agent to remove any native metal oxide or native metal hydroxide from a top surface of the conductive fill. “native” metal oxide and “native” metal hydroxide refers to metal oxide and metal hydroxide that forms uncontrollably from reactants in the ambient, as known to one of ordinary skill in the art of integrated circuit fabrication.
In a first embodiment of the present invention, for forming a self-aligned passivation material of an intermetallic compound at the top surface of the conductive fill, a layer of bulk passivation material is formed over the top surface of the conductive fill in a PVD (plasma vapor deposition)

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