Formation of self-aligned capacitor contact module in stacked cy

Details Formation of self-aligned capacitor contact module in stacked cy Formation of self-aligned capacitor contact module in stacked cy

1996-09-24

1998-06-02

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438397, H01L 218242, H01L 2120

Patent

active

057598924

ABSTRACT:
The present invention provides a method of manufacturing a cylindrical capacitor which has plug spacers that reduce capacitor size and increase overlay tolerances. The method begins by forming an insulating layer and a passivation layer over a substrate. A plug opening is formed through the passivation layer and the insulating layer. A polysilicon plug is formed in the plug opening. Plug opening spacers are formed on the sidewalls of the insulating and passivation layers in the plug opening. A first dielectric layer having a bottom electrode opening is formed over passivation layer and the plug is exposed. A third polysilicon layer is formed over the first dielectric layer and on the sidewalls of the first dielectric layer. A second dielectric layer is formed over the third polysilicon layer and in the bottom electrode opening. The second dielectric layer and the third polysilicon layer are RIE etched down to the level on the top surface of the first dielectric layer. The third polysilicon layer in the electrode opening forms a capacitor bottom electrode over the plug. The first dielectric layer and the second dielectric layer are etched away. The plug spacer and the plug prevent the etch from etching voids in the underlying insulating layer when the bottom electrode is misaligned relative to the plug.

REFERENCES:
patent: 5217914 (1993-06-01), Matsumoto et al.
patent: 5332685 (1994-07-01), Park et al.
patent: 5451539 (1995-09-01), Ryou
patent: 5459094 (1995-10-01), Jun
patent: 5501998 (1996-03-01), Chen

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