Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-02
2006-05-02
Thai, Luan (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S297000
Reexamination Certificate
active
07037792
ABSTRACT:
Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant carbohydrate. In one embodiment, conforming ARC fluid is spun-on and hardened. A selective, dry plasma etches the hardened ARC over the sacrificial oxide while leaving intact part of the ARC that adheres to the trench fill sidewall. The remnant sidewall material defines a protective shroud which delays the subsequent isotropic etchant (e.g., wet HF solution) from immediately reaching the sidewall of the trench fill material. The delay length of the shroud can be controlled by tuning the etchback recipe. In one embodiment, the percent oxygen in an O2plus Cl2plasma and/or bias power during the plasma etch is used as a tuning parameter.
REFERENCES:
patent: 6060371 (2000-05-01), Shinmura
patent: 6337262 (2002-01-01), Pradeep et al.
patent: 6933240 (2005-08-01), Lazar et al.
Haselden Barbara A.
Lee John
MacPherson Kwok & Chen & Heid LLP
Park David S.
ProMOS Technologies Inc.
Thai Luan
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