Formation of memory cells and select gates of NAND memory...

Details Formation of memory cells and select gates of NAND memory... Formation of memory cells and select gates of NAND memory...

2004-06-28

2008-03-25

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21680

Reexamination Certificate

active

07348236

ABSTRACT:
Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing portions of a second conductive layer disposed on a first conductive layer such that remaining portions of the second conductive layer self align with and are disposed on sidewalls of the first conductive layer. The first conductive layer is disposed on a first dielectric layer that is disposed on a substrate. A second dielectric layer is formed overlying the first conductive layer and the remaining portions of the second conductive layer. A third conductive layer is formed on the second dielectric layer. A fourth conductive layer is formed on the third conductive layer. For the select gate, the fourth conductive layer also passes through the third conductive layer and the second dielectric layer to electrically connect the conductive layers.

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