Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-04
2001-11-13
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000
Reexamination Certificate
active
06316299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
An integrated circuit Laterally Diffused Metal-Oxide Semiconductor (LDMOS) power transistor employs a source isolated, embedded gate Metal-Oxide Semiconductor transistor with laterally diffused technology to provide a source isolated high voltage power transistor in applications requiring electrical isolation between the source and substrate.
2. Description of the Prior Art
In the field of power integrated circuits much work has been done in the development of power transistors. Advancements were made enabling Laterally Diffused Metal-Oxide Semiconductor (LDMOS) power transistors to exhibit low “on-resistance” and high breakdown capability concurrently through a reduced horizontal-surface field technique.
In the past, LDMOS transistors commonly were used in low side driver applications because the transistor's structure is coupled with the source to the substrate that in turn was coupled to the ground. Although low side driving configuration consists of the source of LDMOS transistor coupled to ground and the drain coupled to an output load. Therefore, LDMOS transistors were not utilized in high side driver applications and other applications that mandated electrical isolation between the source and substrate. (A high side driver configuration consists of the LDMOS transistor drain coupled to circuitry or a power supply and the source coupled to an output load.)
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming Laterally Diffused Metal-Oxide Semiconductor (LDMOS) that substantially can employ a source isolated high voltage power transistor in applications requiring electrical isolation between the source and substrate.
The present invention for forming a Laterally Diffused Metal-Oxide Semiconductor structure comprises the following steps. First, a silicon oxide layer is formed on a semiconductor substrate. Then, a first doping N-well region is formed in the semiconductor substrate. Next, a second doping N-well region which overlies the first doping N-well region is formed in the semiconductor substrate. Thereafter, a trench isolation is formed into the semiconductor substrate having a depth less than the depth of the first doping N-well region. Then, the silicon oxide layer is removed. Next, a field oxide is grown on the surface at the bottom of the trench. Then, a third N doping region is formed along the entire surface of the pad oxide layer within the trench. Next, the field oxide layer is removed to expose the semiconductor substrate within the trench. Thereafter, a gate oxide layer is formed on the surface of a semiconductor layer with the trench. Next, an N-type polysilicon layer is formed to fill the trench. Last, an N
+
source/drain layer is formed which is located above the second doping N-well region and under the top surface of the semiconductor substrate in order to complete the laterally diffused metal-oxide semiconductor structure.
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Fourson George
Garcia Joannie A.
United Microelectronics Corp.
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