Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-05-11
2001-12-18
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000, C438S595000, C438S653000, C438S776000, C438S786000
Reexamination Certificate
active
06331468
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the production of integrated circuit structures on a semiconductor substrate. More particularly it relates to the use of one or more silicon layers in the formation of defect-free source/drain regions, by implantation and out-diffusion of the one or more silicon layers into the substrate, and later formation of silicon nitride spacers from the one or more silicon layers.
2. Description of the Related Art
As geometries of integrated circuit structures have been reduced, the contribution of defects in a single crystal silicon semiconductor substrate, created during implantation of the substrate to form source/drain regions of an MOS device, gains in importance because such implant-caused crystal defects in a single crystal semiconductor substrate, such as a single crystal silicon substrate, adversely affect the subsequent dopant diffusion in the lightly doped drain (LDD) or heavily doped drain (HDD), and into channel regions of such an MOS device formed in the substrate.
While it is known to implant a sacrificial diffusion layer on a single crystal semiconductor substrate followed by out-diffusion of the dopant from the diffusion layer into the substrate to thereby isolate the implantation-generated defects from the substrate, some manner of protection must be afforded to the channel region of the substrate under the gate electrode during concurrent implantation of a polysilicon gate electrode and then diffusion of the dopant into and through the gate electrode during annealing to concurrently form the source/drain regions in the substrate. This is a particular problem since such dopants may diffuse at a faster rate through the polysilicon gate electrode (toward the underlying channel region) than the dopants diffusing into the single crystal semiconductor deep enough to form the desired source/drain regions.
Pending Aronowitz et al. U.S. patent application Ser. No. 08/816,254, filed by one of us on Mar. 13, 1997, and assigned to the assignee of this invention, the disclosure of which is hereby incorporated by reference, discusses the problems of protecting the underlying channel area of a semiconductor substrate during doping of the gate electrode. The above-referenced Aronowitz et al. patent application suggests and claims the formation of a nitridized silicon barrier layer over the gate oxide and beneath the polysilicon gate electrode by the treating, with a nitrogen plasma, of a thin layer of silicon formed over the gate oxide to thereby form a nitridized silicon dopant barrier layer. This nitridized silicon layer then prevents penetration of the gate electrode dopant through the barrier layer into the gate oxide, and the channel region of the substrate beneath the gate oxide during the annealing step.
While the above-referenced Aronowitz et al. patent application addresses the problem of dopant diffusion into the channel region of a single crystal substrate below the gate electrode, the use of an implant and out-diffusion layer over the substrate and the gate electrode still introduces additional process steps in the formation and subsequent removal of such a layer. While it has been proposed to subsequently use such an implant and out-diffusion layer (when the layer comprises silicon) in the formation of metal silicide contacts, this is not always useful or desirable, thus necessitating removal of the implant and out-diffusion layer after formation of the source/drain regions, which adds to the complexity and expense of the process.
It would be desirable if the problem of implant-caused defects in the substrate could be rectified by the use of an implantation and outdiffusion layer over the substrate which layer could not only be used in the formation of source/drain regions of varying dopant density, but then further used in the formation of a desired component of the integrated circuit structure, other than a metal silicide contact.
SUMMARY OF THE INVENTION
In accordance with the invention, a nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by exposing either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to a nitrogen plasma to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). The resulting polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions.
In another embodiment, the exposed portions of the gate oxide layer are not removed after definition of the polysilicon gate. In this embodiment, the presence of the gate oxide layer under the implanted amorphous silicon layer results in less dopant being diffused into the substrate during the annealing step, thus creating LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant). As in the earlier embodiment, the annealed silicon layer is then exposed to a nitrogen plasma to convert it to a silicon nitride which is then anisotropically etched to form first silicon nitride spacers on the sidewalls of the gate electrode. However, in this embodiment, a further layer of amorphous silicon is then deposited over the structure (after formation of the first silicon nitride spacers), implanted with a further dosage of the same dopant at a higher dosage level than the first implant, and the structure is then annealed to diffuse the further dosage of dopant into the substrate to form the source/drain regions, as well as to convert the second amorphous silicon layer to a polysilicon layer. This resulting second polysilicon layer is then also nitridized to form a further layer of silicon nitride which is then anisotropically etched to form a second set of silicon nitride spacers adjacent and contiguous with the first set of silicon nitride spacers. The resulting structure has doped source/drain regions in the substrate formed from the higher dosage level of implanted dopant in the second amorphous silicon layer, and separated from the channel beneath the polysilicon gate electrode by the less highly doped (e.g., LDD or HDD) regions formed during the first doping of the substrate with the lower dosage of dopant.
In yet a third embodiment of the invention, after formation of the gate oxide, a portion of the gate oxide is masked, leaving an unmasked portion larger than the subsequently formed gate electrode. A barrier layer is then formed over this unmasked portion of the gate oxide, by nitridating the unmasked portion of the gate oxide. The polysilicon gate electrode is then formed, and then an amorphous silicon layer is deposited over the structure. However, in this embodiment, the amorphous silicon layer is then subject to two implants for N channel device formation. A heavy dosage of arsenic is implanted together with a lighter dosage of phosphorus. The structure is then annealed to cause the implanted dopants to diffuse through the gate oxide (where present) into the substrate causing the formation of source/drain layers beneath the doped amorphous sil
Aronowitz Sheldon
Kapre Ravindra A.
Kimball James P.
Puchner Helmut
Chaudhuri Olik
Duy Mai Anh
LSI Logic Corporation
Taylor John P.
LandOfFree
Formation of integrated circuit structure using one or more... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Formation of integrated circuit structure using one or more..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Formation of integrated circuit structure using one or more... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2563417