Formation of highly conductive junctions by rapid thermal...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S303000, C438S305000, C438S306000, C438S307000, C438S308000

Reexamination Certificate

active

06287925

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of integrated circuit devices having scaled-down dimensions, and more particularly, to a method for fabricating highly conductive junctions used, for example, for formation of the drain and the source of a field effect transistor, by performing a rapid thermal anneal before a laser thermal process for effective activation of a high concentration of dopant.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
The present invention is described for formation of highly conductive junctions for a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having scaled down dimensions. However, the present invention may be used to particular advantage for formation of a highly conductive junction as part of other integrated circuit devices having scaled down dimensions, as would be apparent to one of ordinary skill in the art of integrated circuit fabrication from the description herein.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain suicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate structure
118
which may be a polysilicon gate. A gate silicide
120
is formed on the polysilicon gate
118
for providing contact to the polysilicon gate
118
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the polysilicon gate
118
and the gate oxide
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the polysilicon gate
118
and the gate oxide
116
.
As dimensions of the MOSFET
100
are scaled further down to tens of nanometers, the drain extension
104
and the source extension
106
are desired to be abrupt and shallow junctions to minimize short-channel effects of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. In addition, for enhancing the speed performance of the MOSFET
100
with scaled down dimensions, a high dopant concentration with high activation in the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
is desired.
In the prior art, dopant within the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
is activated using a RTA (Rapid Thermal Anneal) process at a relatively lower temperature such as at temperatures less than 1000° Celsius, for example, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as dimensions of the MOSFET
100
are further scaled down, a RTA process is disadvantageous because thermal diffusion of the dopant within the drain extension
104
and the source extension
106
causes the drain extension
104
and the source extension
106
to become less shallow. In addition, with a RTA process, the concentration of the dopant within the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
is limited by the solid solubility of the dopant within the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
, as known to one of ordinary skill in the art of integrated circuit fabrication.
Because of such limitations of using a RTA process to activate dopant within the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
, a laser thermal process is also used as known in the prior art. In such a laser thermal process, the dopant within the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
is activated by directing a laser beam toward the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
.
Activation by such a laser thermal process is advantageous because the time period for heating the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
is on the order of a few nanoseconds (which is approximately eight orders of magnitude shorter than a RTA process). Thus, thermal diffusion of dopant within the drain extension
104
and the source extension
106
is negligible such that the drain extension
104
and the source extension
106
remain shallow, as known to one of ordinary skill in the art of integrated circuit fabrication.
In addition, because the semiconductor material forming the drain extension
104
and the source extension
106
becomes molten and then recrystallizes, the drain extension
104
and the source extension
106
formed by activation using the laser thermal process is an abrupt junction. Furthermore, because the melting and recrystallization time period is on the order of hundreds of nanoseconds, the activated dopant concentration within the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
is well above the solid solubility, as known to one of ordinary skill in the art of integrated circuit fabrication.
Despite such advantages of the laser thermal process, the drain extension
104
, the source extension
106
, the drain contact junction
108
, and the source contact junction
112
formed using the laser thermal process may also have disadvantageous features. For example, when such junctions are activated using the laser thermal process, the interface of such junctions with the semiconductor substrate
102
has crystallization defects, as known to one of ordinary skill in the art of integrated circuit fabrication. Such crystallization defects result in large series resistance at the drain and source of the MOSFET
100
and in turn in degradation of the speed performance of the MOSFET
100
.
Nevertheless, as the MOSFET is further scaled down, a laser thermal process for activating dopant in the drain extension
104
and the source extension
106
of the MOSFET is desired f

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