Formation of fully silicided metal gate using dual...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S383000, C257S384000, C257S412000, C257S413000, C257S347000, C257SE21203, C257SE21439, C257SE21636, C257SE21640, C257SE29178, C257SE29266

Reexamination Certificate

active

10890753

ABSTRACT:
An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

REFERENCES:
patent: 6737710 (2004-05-01), Cheng et al.
patent: 6969678 (2005-11-01), Chiu et al.
patent: 2004/0026688 (2004-02-01), Jang et al.
patent: 2005/0079695 (2005-04-01), Carriere et al.
patent: 2005/0156238 (2005-07-01), Wen et al.
patent: 2005/0269635 (2005-12-01), Bojarczuk et al.
patent: 2006/0006476 (2006-01-01), Biery et al.
patent: 1122771 (2001-08-01), None

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