Formation of dual gate oxide by two-step wet oxidation

Details Formation of dual gate oxide by two-step wet oxidation Formation of dual gate oxide by two-step wet oxidation

1999-04-26

2004-03-16

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S235000, C438S238000, C438S247000, C438S249000

Reexamination Certificate

active

06706577

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating both high and low voltage CMOS transistors in the fabrication of integrated circuits, and more particularly, to a method of fabricating both high and low voltage CMOS transistors simultaneously by forming dual gate silicon oxide layers using a two-step wet oxidation process in the fabrication of integrated circuits.
(2) Description of the Prior Art
With the advent of large scale integration, many of the integrated circuits formed on a semiconductor substrate comprise several circuit functions on a single chip. To optimize the devices and improve performance, it is desirable in the industry to provide field effect transistors (FET) having both thick and thin gate oxide layers thereunder. For example, typically a thin gate oxide is used in peripheral low voltage logic circuits to enhance FET device performance, while a thicker gate oxide is required for the high voltage FET access transistors in a DRAM cell.
The gate oxide thickness is the major issue in terms of reliability considerations in mixing high and low voltage transistors in one device. For example, in a 0.25 micron process, a thin gate oxide of about 40 Angstroms is grown by a dry oxidation process over both high and low voltage areas. This provides the proper gate oxide thickness for a low voltage transistor. A second wet oxidation is performed over the first gate oxide in the high voltage area to provide a thick gate oxide of about 90 Angstroms.
Shallow trench isolation (STI) has become increasingly common as device sizes shrink. Many workers in the art have addressed the problem of trench filling while avoiding dishing and other problems. Co-pending U.S. Patent Application Ser. No. 08/794,597 to S. M. Jang et al, filed on Feb. 3, 1997, discloses filling STI using high density plasma chemically vapor deposited (HDPCVD) oxide and polishing to form planarized STI regions.
For example,
FIG. 1
shows a simplified illustration of a partially completed integrated circuit device in which the low voltage area
3
is shown on the left side of the figure and the high voltage area
5
is shown on the right side of the figure and where, for clarity's sake, a dotted line is shown dividing the low and high voltage areas.
The active areas of the substrate have been isolated from one another by shallow trench isolation (STI) regions
12
. Thin gate oxide
14
has been formed in the low voltage area
3
and thick gate oxide
16
has been formed in the high voltage area
5
.
It has been found that the thicker gate oxide shows poor integrity when HDPCVD oxide has been used to fill the STI regions. That is, the oxide breakdown voltage is low and the defect rate is high. The thicker oxide can trap more defects from the HDPCVD oxide than does the thinner oxide resulting in poorer quality of the thicker oxide. The exact mechanism of poor oxide quality in the presence of HDPCVD oxide is unknown, but it may come from the plasma effect in which many ions, radicals, and free charge electrons are present. It is desired to find a process of forming both thick and thin gate oxide layers on a semiconductor substrate that will have high quality especially in the presence of HDPCVD oxide.
U.S. Pat. No. 5,502,009 to Lin teaches forming a first gate oxide layer using wet or dry oxidation, removing a portion of the first gate oxide layer, and then forming a second thicker gate oxide layer using wet or dry oxidation in O
2
where the first oxidation was removed. U.S. Pat. No. 5,595,922 to Tigelaar et al teaches wet oxidation of a first oxide layer under a gate electrode to form a thicker gate oxide layer. U.S. Pat. No. 5,668,035 to Fang et al discloses forming a first gate oxide by dry oxidation, removing the gate oxide in one area, then forming a second thinner gate oxide by dry oxidation in the area where the first oxide layer was removed. U.S. Pat. No. 5,244,843 to Chau et al and U.S. Pat. No. 5,470,611 to Yang et al teach a dry oxidation followed by a wet oxidation. U.S. Pat. No. 5,538,923 to Gardner et al teaches a dry oxidation. None of these patents mention HDPCVD oxide.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of simultaneously forming both high and low voltage transistors in the fabrication of an integrated circuit.
Another object of the present invention is to provide an effective and very manufacturable method of simultaneously forming differential gate oxide thicknesses for both high and low voltage transistors in the fabrication of an integrated circuit.
Another object of the present invention is to form a dual thickness gate oxide using a two-step wet oxidation.
A further object of the invention is to simultaneously form differential gate oxide thicknesses for both high and low voltage transistors using a two-step wet oxidation in the fabrication of an integrated circuit.
A still further object is to improve the integrity of a dual thickness gate oxide in the fabrication of an integrated circuit.
Yet another object of the invention is to improve the integrity of a dual thickness gate oxide by using a two-step wet oxidation process.
Yet another object is to improve the integrity of a dual thickness gate oxide over shallow trench isolation in the fabrication of an integrated circuit.
Yet another object is to improve the integrity of a dual thickness gate oxide over high density plasma chemically vapor deposited (HDPCVD) oxide shallow trench isolation in the fabrication of an integrated circuit.
In accordance with the objects of this invention a new method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is achieved. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.


REFERENCES:
patent: 5210056 (1993-05-01), Pong
patent: 5244843 (1993-09-01), Chau et al.
patent: 5470611 (1995-11-01), Yang et al.
patent: 5502009 (1996-03-01), Lin
patent: 5538923 (1996-07-01), Gardner et al.
patent: 5595922 (1997-01-01), Tigelaar et al.
patent: 5668035 (1997-09-01), Fang et al.
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patent: 6133119 (2000-10-01), Yamazaki
patent: 9210432 (1992-11-01), None

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