Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-15
2001-01-23
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000
Reexamination Certificate
active
06177698
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to a method for forming deep trench top isolation layers for semiconductor memories by employing a selective sub-atmospheric chemical vapor deposition oxide (SACVD-oxide).
2. Description of the Related Art
Semiconductor memories such as dynamic random access memories (DRAM) typically include memory cells with storage nodes. Generally these storage nodes are formed within deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using an access transistor which allows charge to be stored in the storage node or retrieves charge from the storage depending on whether the desired action is a read or write function. It is often necessary to ensure that the storage node is sufficiently electrically isolated from a gate conductor through the top of the deep trench.
One way to ensure sufficient electrical isolation of the storage node through the top of the trench is to provide a top trench isolation layer over the storage node. The storage nodes typically include polysilicon material that partially fills the deep trench. During fabrication the polysilicon provides a recess remaining at the top of the trench. An oxide (silicon dioxide) is deposited over the surface of the semiconductor device. During the oxide deposition, oxide is formed over the polysilicon in the trench. Other portions of the deposited oxide are removed by planarizing the surface of the semiconductor device and by optionally recessing the oxide to leave a 30-50 nm oxide layer at the bottom of the recess. This oxide layer is referred to as a trench top oxide or isolation. The oxide layer alone may not provide sufficient isolation however to fulfill reliability requirements.
In the case where vertical transistors are fabricated on the memory device, a buried strap portion of the storage node, i.e., the portion directly below the top trench oxide must outdiffuse to connect to a vertical transistor channel which extends along a gate conductor in the deep trench above the top trench oxide. In this way, when the vertical transistor conducts, a connection is made between the storage node and a bit line. The channel must be electrically isolated from the gate conductor. Therefore, an insulating layer is provided therebetween, typically an oxide layer formed by oxidizing a portion of the polysilicon of the gate conductor within the deep trench and the channel.
The oxide recessing is difficult to control. This difficulty introduces a lot of variability in the remaining oxide layer thickness. The trench top oxide thickness is an important parameter and must be maintained in order for the semiconductor memory to work properly. As described above, the trench top oxide electrically isolates the storage node from the gate conductor of the semiconductor device.
Therefore, a need exists for a trench top dielectric having a controlled thickness which can withstand the processing steps needed to fabricate a memory device. A further need exists for a method of providing the trench top isolation using a selective subatmospheric chemical vapor deposition oxide growth process.
SUMMARY OF THE INVENTION
A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the conductive material and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and removing the selective oxide deposition layer except for a portion in contact with the conductive material to form an isolation layer on the conductive material in the trench.
In alternate methods, the step of depositing the selective oxide deposition layer may include depositing the selective oxide deposition layer by chemical vapor deposition. The selective oxide deposition layer may include an ozone activated TEOS oxide and the liner may include a nitride. The increased rate of growing is preferably about five times greater for the conductive material than on the liner of the sidewalls. The step of forming a liner on sidewalls may include forming a nitride liner. The thickness of the selective oxide deposition layer is preferably between about 10 nm to about 200 nm. The conductive material preferably includes polysilicon and may further include the step of densifying the polysilicon below the trench top isolation layer. The step of removing the liner from the trench sidewalls is also preferably included.
A method for fabricating a vertical transistor includes the steps of providing a substrate having trenches formed therein, each trench having a storage node formed therein, the storage node having a buried strap, forming a liner on sidewalls of the trench above the buried strap, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition deposited layer selectively growing at an increased rate on the buried strap as compared to the liner of the sidewalls and removing the selective oxide deposition layer except for a portion in contact with the buried strap to form a trench top isolation layer, removing the liner from the sidewalls and forming a gate conductor in the trench such that a channel is formed adjacent to the gate conductor for providing electrical conduction between the buried strap and a conductive line upon activation of the gate conductor.
In alternate methods, the step of laterally etching the substrate to form a recess into the substrate such that the recess extends beyond sides of the trench may be included, the recess being in communication with the trench. The step of laterally etching may further include laterally etching by a dry etch process. The conductive line may comprise a bitline. The step of depositing the selective oxide deposition layer may include depositing the selective oxide deposition layer by chemical vapor deposition. The selective oxide deposition deposited layer preferably includes an ozone activated TEOS oxide and the liner includes a nitride. The increased rate of growing is preferably about five times greater for the buried strap than on the liner of the sidewalls. The step of forming a liner on sidewalls may include a nitride liner. The thickness of the selective oxide deposition layer is between about 10 nm to about 100 nm on the buried strap. The buried strap includes polysilicon and the step of densifying the polysilicon below the trench top isolation layer may also be included. The step of removing the liner from the trench sidewalls may be included.
A semiconductor memory is also provided which includes a substrate having a plurality of deep trenches formed therein, each deep trench having a buried strap formed therein for accessing a storage node disposed within the deep trench. An isolation layer is formed from a selectively growing a sub-atmospheric chemical vapor deposition material, the sub-atmospheric chemical vapor deposition material layer being formed on the buried strap by growing the sub-atmospheric chemical vapor deposition material layer at a faster rate on the buried strap than on sidewalls of the trench above the buried strap.
In alternate embodiments, the isolation layer preferably includes an an ozone activated TEOS. The thickness of the isolation layer is between about 10 nm to about 200 nm. An access transistor is preferably included and a gate is preferably formed in the trench having at least a portion of the gate in contact with the isolation layer. The transistor may include a channel formed in the substrate adjacent to the gate for electrically coupling the buried strap to a bitline. The substrate may include a recessed portion for enabling increased overlap between outdiffusion from the buried strap and the channel.
These and other objects, features and advantages of the present invention will
Beintner Jochen
Gabric Zvonimir
Gruening Ulrike
Lee Gill
Spindler Oswald
Chaudhuri Olik
Infineon Technologies North America Corp.
Paschburg Donald B.
Peralta Ginette
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