Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-30
2001-09-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S393000, C438S394000
Reexamination Certificate
active
06284594
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process for integrating the processes needed to fabricate a capacitor structure, and a transfer gate transistor, on the same semiconductor chip
(2) Description of Prior Art
To reduce processing costs of memory and logic semiconductor devices, comprised with both polysilicon capacitor structures, and transfer gate transistor, polysilicon gate structures, integration of as many process steps, or process sequences, used for both the capacitor and transfer gate transistor is desirable. However although some process sequences allow the desired process integration, deleterious effects, due to the sharing of process steps and sequences can occur. For example if the capacitor bottom plate, and gate structure, of the transfer gate transistor, are formed during the same process sequence, in addition to the formation of source/drain regions, formed self-aligned to the polysilicon gate structure of the transfer gate transistor, the temperature needed for formation of a capacitor dielectric layer, on the surface of the polysilicon bottom plate, of the capacitor, can result in unwanted movement of dopants in the transfer gate transistor region. If the polysilicon gate structure is formed after formation of the polysilicon bottom plate, the topography created by the bottom plate structure may result in difficulties when patterning the polysilicon gate structure, using anisotropic reactive ion etching procedures, resulting in unremoved polysilicon ribbons and residues, possibly resulting in a conductive path allowing leakage or shorts, between specific devices to occur.
This invention will describe a novel process sequence allowing integration of many process steps, and sequences, used for both the capacitor structure and a transfer gate transistor, to be shared. Featured in this invention is the creation of a polysilicon bottom plate, embedded in insulator, formed by a chemical mechanical polishing, (CMP), procedure, prior to formation of a polysilicon gate structure, of a transfer gate transistor. Also featured in this invention is the formation of the well regions, and the source/drain regions, in a epitaxial silicon layer, selectively grown on the semiconductor substrate, in an opening in the same insulator layers that the capacitor bottom plate resides on. This allows, after the growth of a gate insulator layer, on the epitaxial silicon layer, in the transfer gate transistor region, as well as the formation of an capacitor dielectric layer, on the capacitor bottom plate, the simultaneous formation of a polysilicon gate structure, on the gate insulator layer, and of a upper polysilicon plate structure, on the capacitor dielectric layer. Prior art, such as Huang, in U.S. Pat. No. 5,924,011, as well as Chen et al, in U.S. Pat. No. 5,607,873, describe processes for forming a capacitor structure, over a field oxide region, however these prior arts do not describe the key features of this present invention, which include: a polysilicon bottom plate, embedded in an insulator layer, via a CMP procedure; the simultaneous formation of a top polysilicon plate, and a polysilicon gate structure; and the use of a selectively grown epitaxial silicon, for the channel region of the transfer gate transistor.
SUMMARY OF THE INVENTION
It is an object of this invention to form a transfer gate transistor, and a capacitor structure, on the same semiconductor substrate, featuring the simultaneous formation of the polysilicon gate structure, of the transfer gate transistor, and the polysilicon top plate, of the capacitor structure.
It is another object of this invention to use a CMP procedure, to form the polysilicon capacitor bottom plate, embedded in an insulator layer.
It is still another object of this invention to use a selective epitaxial growth, (SEG), procedure to form an active device silicon region, in an opening in a composite insulator layer, resulting in a planar top surface topography comprised of the embedded, polysilicon capacitor bottom plate, and the active device silicon region, allowing the subsequent formation of an overlying polysilicon gate structure, and an overlying polysilicon capacitor top plate, to be formed on the planar, underlying topography.
In accordance with the present invention a method of forming a transfer gate transistor, and a capacitor structure, on the same semiconductor chip, featuring the simultaneous formation of the polysilicon gate structure, of the transfer gate transistor, and the polysilicon top plate, of the capacitor structure, is described. A polysilicon bottom plate, of a subsequent capacitor structure, is embedded in a first opening in a portion of a composite insulator layer, via deposition of a polysilicon layer, followed by a CMP procedure. A selectively grown, epitaxial silicon layer is next formed in a second opening in the composite insulator layer, located in a subsequent transfer gate transistor region, resulting in a planar top surface topography comprised of the polysilicon bottom plate, of the capacitor structure, and the transfer gate transistor, epitaxial silicon region. After formation of well regions, as well as the formation of threshold adjust, and punch through regions, creating an active device region, in the epitaxial silicon region, a gate insulator layer is grown on the top surface of the epitaxial silicon region, while the same oxidation procedure forms the capacitor dielectric layer, on the polysilicon bottom plate. A polysilicon layer is deposited and patterned creating both a polysilicon gate structure, on the gate insulator layer, and a polysilicon top plate, on the capacitor dielectric layer. Source/drain regions, are then formed in regions of the active device region of the transfer gate transistor, not covered by the polysilicon gate structure, in addition to the formation of insulator spacers on the sides of the polysilicon gate structure and the polysilicon top plate.
REFERENCES:
patent: 5607873 (1997-03-01), Chen et al.
patent: 5804488 (1998-09-01), Shih et al.
patent: 5866451 (1999-02-01), Yoo et al.
patent: 5891763 (1999-04-01), Wamlass
patent: 5924011 (1999-07-01), Huang
patent: 6184927 (2001-02-01), Kang
Chu Shao-Fu Sanford
Ju Yong
Shao Kai
Wang Yimin
Chartered Semiconductor Manufacturing Ltd.
Le Dung A
Nelms David
Pike Rosemary L. S.
Saile George O.
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