Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-20
2004-08-10
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S434000, C438S435000, C438S437000, C438S448000
Reexamination Certificate
active
06773975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
Shallow trench isolation (STI) structures are employed to isolate integrated circuit elements in a semiconductor wafer. A conventional STI process includes the steps of etching a trench in a silicon substrate, filling the trench with a gap fill oxide, and chemical-mechanical polishing (CMP) of the gap fill oxide. For metal oxide semiconductor (MOS) transistors, transistor gates are formed in active regions of the wafer typically after the formation of STI structures. STI has gained popularity because it allows for higher device density than LOCOS isolation. STI, however, is not without its share of problems.
One problem with conventional STI processes is that sharp corners of active areas adjacent to the trenches are likely to get exposed during subsequent processing steps. A sharp corner may result in parasitic transistor behavior, such as excessive corner current leakage and inverse narrow width effect. In addition, polysilicon employed as transistor gate material may get deposited in a trench corner and form poly stringers after a gate etch step. Poly stringers are known to cause shorted connections in integrated circuits.
SUMMARY
In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.
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Schwalke, U., et al. “Comer-Parasitics-Free Low-Cost Trench Isolation”, IEEE Electron Device Letters, Nov. 1999, vol. 20, No. 11; Munich, Germany.
Schwalke, Udo, et al. “Exitgate: The Ultimate Process Architecture for Submicron CMOS Technologies” IEEE Transactions on Electron Devices, Nov. 1997, vol. 44, No. 11; Munich, Germany.
Narayanan Sundar
Ramkumar Krishnaswamy
Sharifzadeh Shahin
Cypress Semiconductor Corporation
Novacek Christy
Okamoto & Benedicto LLP
Zarabian Amir
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