Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-27
2001-09-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S598000, C438S599000, C438S618000, C438S621000
Reexamination Certificate
active
06284591
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming an interconnection in a semiconductor device, and relates more particularly, to a method of forming an interconnection in such a device by using a landing pad.
Interconnection technology in a semiconductor device can be divided into two steps, i.e., formation of a contact hole and formation of an interconnection. As a semiconductor device becomes high-integrated, a width of the interconnection line becomes more narrow. Furthermore, when the horizontal size of the contact is reduced, its vertical size is increased, which increases the aspect ratio of the contact. A metal interconnection must be multileveled to enable the enhancing of the operation speed of a device and to provide for a reliable interconnection. In addition, the filling of a contact hole is essential for the planarization of an interdielectric layer.
The filling techniques for filling contact holes in current multilevel interconnection formation processes consist mainly of either one of two methods. Such filling procedures usually involve either a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method.
The PVD method involves depositing a metal such as aluminum in the contact hole by sputtering. However, when the aspect ratio increases because of the reduction of a contact hole size, e.g., to 1 &mgr;m or less, the step coverage of a metal deposited on the contact hole is degraded.
The CVD method of filling a contact hole is advantageous for obtaining excellent step-coverage characteristic. However, the CVD method still presents difficulties when the method involves depositing aluminum in the contact hole.
As the aspect ratio of the contact hole increases because of the high-integration of a semiconductor, e.g., as you move to a 256M DRAM and a 1G DRAM, it is difficult to fill the contact hole. This difficulty is present even when a new aluminum reflow method is used to fill the contact hole for the formation of the metal interconnection layer.
Accordingly, due to the difficulties in filling the contact holes, the step-coverage of the metal interconnection is degraded and the contact resistances are increased.
SUMMARY OF THE INVENTION
An object of the present invention to provide a method of forming an interconnection using a landing pad for lowering an aspect ratio of a contact to permit an aluminum (Al) reflow process to be effectively applied to a contact that is horizontally narrow and vertically deep.
To accomplish the above object of the present invention, there is provided a method of forming an interconnection in a semiconductor device having a memory cell portion and a peripheral circuit portion, the method comprising: forming an active region of the memory cell portion, forming an active region of the peripheral portion, forming a gate electrode over a silicon substrate, depositing a first insulating film over the gate electrode and the silicon substrate, forming a recess structure connected to the active region of the memory cell portion by etching the first insulating film, forming a contact hole for landing pad formation connected to the active region of the peripheral circuit portion by etching the first insulating film, depositing a metal layer over the first insulating film, the recess structure, and the contact hole, depositing a metal compound layer over the metal layer, the first insulating film, the recess structure, and the contact hole, depositing a metal material layer over the metal layer, the first insulating film, the recess structure, and the contact hole, to fill the recess structure and the contact hole, and removing portions of the metal compound layer and the metal material layer not in the recess structure and the contact hole to form a bitline and a landing pad.
The first insulating film may comprise a silicon oxide material. The first insulating film is preferably formed by chemical vapor deposition or high density plasma deposition.
In preferred method for forming an interconnection, after depositing the metal layer and before depositing the metal compound layer, the process may further comprise selectively forming an ohmic contact layer over the surface of the silicon substrate by reacting the metal layer with silicon and stripping away a non-reacted portion of the metal layer.
The recess structure may be formed by etching the first insulating film in multiple stages. The recess structure and the contact hole are preferably simultaneously formed on a P-type portion and an N-type portion of the active region.
The metal layer preferably comprises a material selected from the group consisting of Ti, W, Mo, Ta, Zr, Ni, and Co, and is preferably formed by sputtering or chemical vapor deposition. The metal compound layer preferably comprises a material selected from the group consisting of TiN, WN, TaN, ZrN, TiC, WC, TaC, and ZrC. The metal material film preferably comprises a material selected from the group consisting of Cu, Al, W, Mo, Ta, Ti, Zr, a nitride of a refractory metal and carbide, and a refractory metal, and is preferably formed by chemical vapor deposition.
The elimination of the metal compound film and the metal material film is preferably performed by chemical mechanical polishing or an etchback process.
In a preferred method for forming an interconnection, after depositing the metal compound layer, the process may further comprise annealing the metal layer to form an ohmic contact.
According to the method of forming an interconnection of the above-mentioned present invention, the landing pad on the peripheral circuit portion is concurrently formed with the bitline in the memory cell portion during manufacturing a memory device, e.g., a DRAM device. Such concurrent formation has the effect of reducing the thickness of an insulating film that can be obtained during a successive step of forming a contact hole for interconnection. As a result, it is easy to etch the insulating film when forming the contact hole and so a contact hole having a small aspect ratio can be formed on the landing pad.
The above mentioned process makes it easier to fill the contact hole for interconnection by an Al reflow method when forming a metal interconnection layer. In addition, the step-coverage of a metal deposited on the contact hole for interconnection is enhanced and contact resistance is reduced. As a result, the reliability of a semiconductor device is increased by producing by such a process.
REFERENCES:
patent: 6001683 (1999-12-01), Lee
Gurley Lynne A.
Jones Volentine PLLC
Niebling John F.
Samsung Electromics Co., Ltd.
LandOfFree
Formation method of interconnection in semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Formation method of interconnection in semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Formation method of interconnection in semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2498873