Formally deriving a minimal clock-gating scheme

Details Formally deriving a minimal clock-gating scheme Formally deriving a minimal clock-gating scheme

2008-04-23

2010-12-07

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07849428

ABSTRACT:
The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.

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patent: 2008/0028347 (2008-01-01), Hiraoglu et al.
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