Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1987-06-24
1989-01-03
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365207, 307449, G11C 700
Patent
active
047962305
ABSTRACT:
A folded cascode configured current steering decoder circuit for coupling a column of memory cells of a static random access memory for reading by a sense amplifier. A pair of cascode configured p-channel transistors turn on to couple memory bit lines to output lines so that the sense amplifier can provide the reading of contents of the selected memory cell. A second pair of p-channel transistors are each coupled to each of the bit lines for providing a steady state current source when the first pair of transistors are turned on for transferring information from the bit line to the output line pairs. The cascode configured transistors are MOSFET switches which are biased to cause a current inbalance when data from the memory cell are placed on the bit lines. The inbalanced current passing through the cascoded transistor pairs causes a current difference which can then sensed by a low input impedence sense amplifier. The cascoded MOSFETS provide for an isolation of the bit line capacitance from the output line capacitance to reduce the amount of time required for transferring information from the bit line to the sense amplifier.
REFERENCES:
patent: 4096584 (1978-06-01), Owen, III et al.
patent: 4284958 (1981-08-01), Pryor et al.
patent: 4284959 (1981-08-01), Heagerty et al.
patent: 4658160 (1987-04-01), Young
Intel Corporation
Moffitt James W.
LandOfFree
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