Flood mode implementation for continuous bitline local...

Details Flood mode implementation for continuous bitline local... Flood mode implementation for continuous bitline local...

2006-11-07

2006-11-07

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S203000

Reexamination Certificate

active

07133320

ABSTRACT:
A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

REFERENCES:
patent: 6275427 (2001-08-01), Aipperspach et al.
patent: 6643804 (2003-11-01), Aipperspach et al.
patent: 6657886 (2003-12-01), Adams et al.
patent: 6728912 (2004-04-01), Dawson et al.
patent: 6901003 (2005-05-01), Adams et al.

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