Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-08-02
2011-08-02
Lee, Calvin (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S317000
Reexamination Certificate
active
07989289
ABSTRACT:
Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.
REFERENCES:
patent: 6265292 (2001-07-01), Parat et al.
patent: 6518618 (2003-02-01), Fazio et al.
patent: 6812515 (2004-11-01), Rabkin et al.
patent: 6943071 (2005-09-01), Fazio et al.
patent: 7183162 (2007-02-01), Soss et al.
patent: 7187591 (2007-03-01), Fastow et al.
patent: 7485526 (2009-02-01), Mouli et al.
patent: 7745874 (2010-06-01), Lee et al.
patent: 2009/0140317 (2009-06-01), Rosmeulen
Pangal, Kiran et al., “Enabling Flash Cell Scaling by Shaping of the Floating Gate Using Spacers”, U.S. Appl. No. 11/728,829, filed Mar. 27, 2007.
Krishnamohan, Tejas et al., “Non-Volatile Memory Cell With Multi-Layer Blocking Dielectric”, U.S. Appl. No. 11/771,482, filed Jun. 29, 2007.
Min, Kyu S., “Self-Aligned Charge-Trapping Layers for Non-Volatile Data Storage, Processes of Forming Same, and Devices Containing Same”, U.S. Appl. No. 11/693,925, filed Mar 30, 2007.
Min, Kyu S., et al., “High-K Trilayer Dielectric Device and Methods”, U.S. Appl. No. 11/694,059, filed Mar. 30, 2007.
Gowda Srivardhan
Graettinger Thomas M.
Krishnamohan Tejas
Min Kyu
Parat Krishna
Cool Patent P.C.
Curtin Joseph P.
Intel Corporation
Lee Calvin
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