Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-07-01
2001-05-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06235581
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to floating gate memory structures in integrated circuits, and more particularly, to a floating gate memory structure and method for forming a low resistance continuous source line.
BACKGROUND OF THE INVENTION
Modern nonvolatile memories include EEPROM devices, such as flash memories that employ a floating gate structure. Memory cells within these devices use channel-hot electrons for programming from the drain side and use Fowler-Nordheim tunneling for erasure from the source side. The gate structure for these devices is typically a stack configuration comprising a floating gate and a control gate separated by an insulation layer.
An existing process used to isolate adjacent conventional flash memory cells is the LOCOS isolation process. Flash memories with LOCOS isolation employ a self-aligned source etch (SAS) and ion implantation to form a continuous source line. The continuous source line normally connects the source of each flash memory cell in a column of the memory and is used for erasing the cells of the memory. To form a continuous source line, a conductive path is created between the source region of adjacent cells so as to create an electrical connection between the adjacent source regions. Preferably, the electrical path through the isolation region is a low resistance path.
More recently, another isolation process has been used to create the isolation region between flash memory cells, especially for embedded memory applications. This process is known as shallow trench isolation (STI), so named because the process results in narrow rectangular trenches between adjacent memory cells. Because of the steepness of the trench walls created by the shallow trench isolation process, it is difficult to use ion implantation in the isolation region, yet maintain a self-aligned source region with a low sheet resistance. The effectiveness of the ion implantation process depends upon the sidewall slope and depth of the trench and control of that process will be difficult to achieve.
To overcome the difficulties of using ion implantation to dope the sidewalls of trench isolation regions, tilt angle ion implantation has been attempted. Unfortunately, tilt angle ion implantation may require the use of multiple energy levels, making the resulting process difficult to control. Also, several tilt angles may need to be used to properly dope the sidewalls of the trench isolation region. The semiconductor processing equipment used for ion implantation must be adjusted for each tilt angle employed in the process. Such adjustment can be time consuming and may require processing to be stopped temporarily for such adjustment to take place. Tilt angle ion implantation may thus substantially increase the cost of flash memory structures in integrated circuits employing shallow trench isolation.
Accordingly, a need has arisen for a processing method which provides for the doping of a trench isolation region so as to form a low resistance continuous source line in a floating gate memory structure.
SUMMARY OF THE INVENTION
The invention employs a silicate glass layer containing an N-type dopant to dope trench sidewalls in a floating gate memory structure. One aspect of the invention is a method for forming a continuous source line. A plurality of trenches and a plurality of moats are formed in a semiconductor structure wherein the plurality of moats are adjacent to the plurality of trenches and a portion of each of the plurality of moats forms the source region of a transistor. A silicate glass layer containing an N-type dopant is deposited outwardly from the semiconductor structure to form an intermediate structure. The intermediate structure is heated for a period of time to dope the plurality of trenches wherein portions of the doped plurality of trenches form a part of at least one continuous source line.
The invention has several important technical advantages. The invention allows greater control over the doping of the continuous source line in a floating gate memory structure, leading to more efficient devices. The invention saves time during the manufacturing process and simplifies that process, thus lowering the cost of manufacturing a floating gate memory device employing a shallow trench isolation process.
REFERENCES:
patent: 5696010 (1997-12-01), Malhi
patent: 5972741 (1999-10-01), Kubo et al.
Brady III Wade James
Garner Jacqueline J.
Hoang Quoc
Nelms David
Telecky , Jr. Frederick J.
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