Flip-flop circuit having scan function

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

Reexamination Certificate

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Details

C326S093000, C326S095000, C326S097000

Reexamination Certificate

active

07994823

ABSTRACT:
A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal.

REFERENCES:
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5898330 (1999-04-01), Klass
patent: 6448829 (2002-09-01), Saraf
patent: 6741113 (2004-05-01), Tang et al.
patent: 7088144 (2006-08-01), Tang et al.
patent: 7157930 (2007-01-01), Hirata
patent: 7345519 (2008-03-01), Hirata
patent: 7712002 (2010-05-01), Baba

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