Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
1999-11-08
2001-07-17
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S778000, C438S108000
Reexamination Certificate
active
06262489
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor integrated circuit (IC) devices. More particularly, this invention relates to a method and structure for providing a backside electrical contact to an IC device chip in which a vertical IC device is formed.
BACKGROUND OF THE INVENTION
As well known in the electronics industry, a flip chip is an unpackaged integrated circuit (IC) chip having bond pads on which solder bumps are formed, with its active side (the surface of the chip containing the active circuit devices and bonding pads) oriented face down toward the circuit substrate, such as a printed circuit board (PCB), to which the flip chip is attached with the solder bumps. Attachment is by registering and reflow soldering the solder bumps to a conductor pattern on a substrate. An advantage of flip chips is that they allow the direct attachment of semiconductor integrated circuits to circuit boards, eliminating the need for an interfacing package.
The usage of flip chips is increasing in the electronics industry. For some applications, vertical devices such as field effect transistors (FET) are required. As known in the art, vertical IC devices are characterized by current flow through the thickness of the device chip. In the past, chips with vertical circuit devices have required wire bonding or specialized packaging. One packaging approach is to solder the device chip to a copper slug having input/output (I/O) pads wirebonded to a leadframe on a substrate. In addition to making electrical connections, the copper slug serves as a heatsink for the device. While suitably performing the intended purpose, significant additional process and material costs are incurred with such packaging practices. Accordingly, it would be desirable if a method were available by which vertical IC devices could be mounted to a substrate without conventional packaging. It would be particularly desirable if such a method could benefit from the assembly and processing advantages available with flip chip technologies.
SUMMARY OF THE INVENTION
The present invention is directed to a method and assembly for mounting a vertical IC semiconductor device to a substrate using flip chip technology. In addition to providing electrical contacts to opposite sides of the device, the assembly also provides a heat dissipation function.
The assembly of this invention generally entails a flip chip having a first surface, an oppositely-disposed second surface, an integrated circuit on the first surface, and an electrical contact on the second surface. According to a preferred aspect of this invention, the integrated circuit may include a vertical device such as an FET, so that current flows through the flip chip between its first and second surfaces. The flip chip is bonded with first solder connections to a first conductor pattern on a suitable substrate, so that the first solder connections electrically and mechanically connect the flip chip to the substrate. The assembly further includes an electrical contact member that is positioned so that the flip chip is between the electrical contact member and the substrate. The electrical contact member is electrically and mechanically connected to a second conductor pattern on the substrate with second solder connections. Finally, a third connection electrically and mechanically connects the electrical contact member to the electrical contact on the second surface of the flip chip.
In a preferred embodiment, the electrical contact member is formed to include a first portion joined to the flip chip and a second portion joined to the substrate, with the first portion having a lower coefficient of thermal expansion (CTE) than the second portion. According to this aspect of the invention, the use of a lower CTE material in the vicinity of the flip chip serves to reduce stress levels that would otherwise significantly reduce the fatigue life of the assembly, and particularly the joint between the contact member and the flip chip.
From the above, one can see that the assembly of this invention is able to provide an uncomplicated method for mounting and attaching a vertical IC device and a backside electrical contact to a substrate using flip chip technology. As with conventional flip chip methods, the flip chip is mounted to the substrate with its electrical contact facing away from the substrate, its integrated circuit facing the substrate, and its solder bumps registered with the first conductor pattern on the substrate. The electrical contact member is then positioned on the substrate so that the flip chip is between the electrical contact member and the substrate. Thereafter, both the flip chip and the contact member are reflow soldered to the substrate, forming the first and second solder connections. In addition, the contact member is joined, preferably reflow soldered, to the flip chip, forming the third connection that electrically and mechanically connects the contact member to the electrical contact on the flip chip.
In addition to making a reliable and fatigue-resistant electrical contact with the flip chip, a benefit of the third connection is that it can be used to draw the flip chip toward the contact member during reflow soldering. In this manner, the contact member prevents the first solder connections of the flip chip from collapsing during reflow soldering, as can occur if the surface tension of the molten solder draws the flip chip excessively close to the substrate during reflow. Sufficient spacing between a flip chip and its substrate, known as the “stand-off height,” is desirable for enabling stress relief during thermal cycles, allowing penetration of cleaning solutions for removing undesirable processing residues, and enabling the penetration of mechanical bonding and underfill materials between the chip and its substrate. As such, the assembly method of this invention promotes the life of the flip chip assembly by helping to control the final height of the first solder connections.
Other objects and advantages of this invention will be better appreciated from the following detailed description.
REFERENCES:
patent: 3972062 (1976-07-01), Hopp
patent: 5371404 (1994-12-01), Juskey et al.
patent: 5619070 (1997-04-01), Kozono
patent: 5650918 (1997-07-01), Suzuki
patent: 6124636 (2000-09-01), Kusamitsu
patent: 6144101 (2000-11-01), Akram
Brandenburg Scott David
Delheimer Charles I
Koors Mark Anthony
Oberlin Gary Eugene
Vajagich Robert
Clark Sheila V.
Delphi Technologies Inc.
Funke Jimmy L.
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