Flip-chip type semiconductor device

Details Flip-chip type semiconductor device Flip-chip type semiconductor device

2000-02-07

2001-05-01

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified encapsulant

C257S783000, C257S795000, C257S778000

Reexamination Certificate

active

06225704

ABSTRACT:

This invention relates to a flip-chip type semiconductor device having a semiconductor chip mounted on a circuit pattern-bearing surface of a substrate via a plurality of bumps, the gap between the substrate and the semiconductor chip being filled with an underfill material and flanked with a fillet material.
BACKGROUND OF THE INVENTION
With the advance of electric equipment toward smaller size, lighter weight and higher performance, the semiconductor mounting technology has changed from the pin mating type to the surface mounting which now becomes the mainstream. One bare chip mounting technology is flip-chip (FC) mounting. The flip-chip mounting is a technique of providing an LSI chip on its circuit pattern-bearing surface with several to several thousands of electrodes, known as bumps, of about 10 to 100 microns high and joining the chip to electrodes on a substrate with a conductive paste or solder. Then the sealing material used for the protection of FC devices must penetrate into gaps of several tens of microns defined by bumps between the substrate and the LSI chip. Conventional liquid epoxy resin compositions used as the underfill material for flip-chip devices are generally composed of a liquid epoxy resin, a curing agent and an inorganic filler. Of these, the most predominant is a composition in which a large amount of inorganic filler is blended in order to provide a matching coefficient of linear expansion with those of semiconductor chips, substrates and bumps for increased reliability.
The flip-chip underfill materials with high loading of filler, however, suffer from very low productivity since they have a high viscosity due to the high filler loading so that they may penetrate into the gap between chip and substrate at a very slow rate. There is a desire to overcome this problem. Also recently, as semiconductor chips become large sized, more attention must be paid to the problem that not only chip cracks, but also fillet cracks occur during solder reflow, despite a matching of expansion coefficient among semiconductor chip, sealing material, organic substrate and solder bumps.
SUMMARY OF THE INVENTION
An object of the invention is to provide a flip-chip type semiconductor device wherein the gap between a chip and a substrate is filled with an underfill material in the form of a liquid epoxy resin composition having a good interstitial infiltration capability and sealed along sides thereof with a fillet material having a lower coefficient of expansion than the underfill material whereby the device becomes more reliable, especially against a thermal shock test.
It has been found that a highly reliable flip-chip type semiconductor device is obtainable using an underfill material having a coefficient of thermal expansion (CTE) of 20 to 40 ppm/° C. at temperatures below its glass transition temperature (Tg) in combination with a fillet material having a CTE of up to 20 ppm/° C. at temperatures below its Tg.
The invention provides a flip-chip type semiconductor device comprising a substrate having a wiring pattern-bearing surface and a semiconductor chip mounted on the wiring pattern-bearing surface via a plurality of bumps to define a gap between the substrate and the semiconductor chip, the gap being filled with an underfill material and sealed along sides thereof with a fillet material. The underfill material is a cured product of a first epoxy resin composition comprising a liquid epoxy resin and an inorganic filler, the cured product having a CTE of 20 to 40 ppm/° C. at temperatures below its Tg. The fillet material is a cured product of a second epoxy resin composition comprising a liquid epoxy resin and an inorganic filler, the cured product having a CTE of up to 20 ppm/° C. at temperatures below its Tg.
In the disclosure, the coefficient of thermal expansion is often abbreviated as CTE, and the glass transition temperature abbreviated as Tg.


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patent: 6081038 (2000-06-01), Murayama
patent: 6100597 (2000-08-01), Nakamura
patent: 6137183 (2000-10-01), Sako

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