Flip chip packages

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257SE23012

Reexamination Certificate

active

07956452

ABSTRACT:
Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.

REFERENCES:
patent: 6534422 (2003-03-01), Ichikawa et al.
patent: 6911736 (2005-06-01), Nagarajan
patent: 7324317 (2008-01-01), Hill et al.
patent: 7518230 (2009-04-01), Miyata et al.
patent: 2003/0235019 (2003-12-01), Ker et al.
patent: 2004/0119159 (2004-06-01), Takahashi
patent: 2005/0230746 (2005-10-01), Eden et al.
patent: 2007/0145565 (2007-06-01), Miyata et al.
patent: 2008/0024102 (2008-01-01), Hebert et al.
patent: 2009/0079071 (2009-03-01), Webb
patent: 2009/0096435 (2009-04-01), Ueunten
patent: 2009/0267085 (2009-10-01), Lee et al.
patent: 2009/0278998 (2009-11-01), El-Ghoroury et al.
patent: 2010/0164079 (2010-07-01), Dekker et al.

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