Flip-chip on flex for high performance packaging applications

Details Flip-chip on flex for high performance packaging applications Flip-chip on flex for high performance packaging applications

2000-03-29

2002-04-02

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

On insulating carrier other than a printed circuit board

C257S723000

Reexamination Certificate

active

06365962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit package that contains a flexible circuit board.
BACKGROUND INFORMATION
Integrated circuits (IC's) are typically assembled into a package that is mounted to a printed circuit board. The printed circuit board may be the motherboard of a computer. The integrated circuit may be mounted to a substrate and encapsulated with a plastic or epoxy material. A process known to those skilled in the art as flip-chip technology may be used to attach an IC to a substrate with the IC's I/O (input/output) side facing the substrate. One method that may be used to attach the flip-chip to the substrate is known as C
4
attachment (controlled-collapse chip connection). With C
4
, solder bumps are placed on metal terminals on the flip-chip and a matching area of solder terminals on the substrate. The flip-chip is then aligned to the substrate, and all solder connections are made simultaneously by reflowing the solder. The substrate is typically a printed circuit board that has a number of pins, known as pin grid array (PGA), or solder balls, known as a ball grid array (BGA), that can be connected to the motherboard.
The substrate contains a number of routing traces, vias and solder pads that electrically connect the integrated circuit to the motherboard. The routing traces and solder pads may be separated by one or more layers of dielectric material.
The substrate/printed circuit board is fabricated before the integrated circuit is mounted to the substrate. The substrate must be thick enough to provide enough structural integrity to support the integrated circuit during the mounting process.
For CMOS (complementary metal oxide semiconductor) logic application, the IC chip integrated into a single package is typically accomplished through a multi-chip module using a 2-dimensional array. This type of package, however, suffers from longer inter-chip connection length. Some of the problems arising from such a package are: high propagation delay, high inductance, and cross-talking noise. In a case where a 3-dimensional array integration package is used, chips are stacked on top of each other and the inter-chip interconnection is achieved through edge wire bonding. A problem with this type of package is that the total I/O is limited.
In an array interconnect package, alignment and attachment are typically difficult to accomplish. For de-coupling needs, discrete de-coupling capacitors are typically mounted on the die-side or landside of the package after die attachment. For die-side capacitors, a larger package is typically required which increases cost. For landside capacitors, a typical package has a large die-to-capacitor separation and a large current loop, which leads to large inductance and degraded system performance.


REFERENCES:
patent: 5642262 (1997-06-01), Terrill et al.
patent: 5998859 (1999-12-01), Griswold et al.

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