Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2005-09-27
2005-09-27
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C138S112000, C138S116000, C138S123000, C138S124000
Reexamination Certificate
active
06949410
ABSTRACT:
A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
REFERENCES:
patent: 4678358 (1987-07-01), Layher
patent: 5105536 (1992-04-01), Neugebauer et al.
patent: 5147821 (1992-09-01), McShane et al.
patent: 5250841 (1993-10-01), Sloan et al.
patent: 5319242 (1994-06-01), Carney et al.
patent: 5347709 (1994-09-01), Maejima et al.
patent: 5637916 (1997-06-01), Joshi
patent: 5654206 (1997-08-01), Merrill
patent: 5723900 (1998-03-01), Kojima et al.
patent: 5765280 (1998-06-01), Joshi
patent: 5789809 (1998-08-01), Joshi
patent: 6018686 (2000-01-01), Orso et al.
patent: 6133634 (2000-10-01), Joshi
patent: 6198163 (2001-03-01), Crowley et al.
patent: 6214640 (2001-04-01), Fosberry et al.
patent: 6215176 (2001-04-01), Huang
patent: 6294403 (2001-09-01), Joshi
patent: 6307755 (2001-10-01), Williams et al.
patent: 6384492 (2002-05-01), Iversen et al.
patent: 6399418 (2002-06-01), Glenn et al.
patent: 6429509 (2002-08-01), Hsuan
patent: 6448110 (2002-09-01), Chen et al.
patent: 6452278 (2002-09-01), DiCaprio et al.
patent: 6469384 (2002-10-01), Joshi
patent: 6489678 (2002-12-01), Joshi
patent: 6528880 (2003-03-01), Planey
patent: 6566749 (2003-05-01), Joshi et al.
patent: 6627991 (2003-09-01), Joshi
patent: 6633030 (2003-10-01), Joshi
patent: 6661082 (2003-12-01), Granada et al.
patent: 6683375 (2004-01-01), Joshi et al.
patent: 6696321 (2004-02-01), Joshi
patent: 6720642 (2004-04-01), Joshi et al.
patent: 6731003 (2004-05-01), Joshi et al.
patent: 2003/0025183 (2003-02-01), Thornton et al.
“IR'S New Synchronous Rectifier Chip Set Meets New Efficiency Standard for DC-DC Converters to Power Notebook PC Processors through 2000.” International Rectifier Company Information. Retrieved from the World Wide Web on Sep. 9, 2003 at http://www.irf.com/whats-new
r990402.html.
U.S. Appl. No. 10/702,792, filed Nov. 5, 2003.
Joshi Rajeev
Manatad Romel N.
Tangpuz Consuelo N.
Brewster William M.
Fairchild Semiconductor Corporation
Townsend and Townsend / and Crew LLP
LandOfFree
Flip chip in leaded molded package and method of manufacture... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip chip in leaded molded package and method of manufacture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip chip in leaded molded package and method of manufacture... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3425506