Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-12-12
2004-11-09
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S789000, C257S790000, C257S737000, C257S738000
Reexamination Certificate
active
06815831
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to integrated circuit (“IC”) packaging, in particular to dies and IC assemblies using underfill.
2. Related Art
Flip chips are surface-mounted chips having connecting metal lines attached to pads on the underside of the chips. A chip or die is typically mounted on an IC substrate to form an IC assembly. For example, a flip chip may be mounted on a package substrate and the resulting package mounted on a printed circuit board (“PCB”). A flip chip may also be directly mounted to a PCB.
Underfill is provided between the chip and the IC substrate to support the electrical connections, to protect them from the environment, and to reduce the thermomechanical stress on the flip chip connection. Underfill materials generally have different coefficients of thermal expansion (“CTE”) from chip and substrate components, e.g., solder connections. This CTE mismatch can lead to thermomechanical stresses that can cause device failure. To avoid this problem, it is desirable for the underfill and other components to have similar CTEs. Underfill CTE may be adjusted by blending filler materials into the underfill. However, dispensing underfill involves long throughput time and acts as a bottleneck in the assembly process. If an underfill has high filler content, it may be difficult to distribute the underfill in a capillary or dispense flow process, especially when a small gap separates the chip and the substrate.
In conventional “no flow” underfill processes, underfill is applied to the surface of an IC substrate. To join a die to the substrate, the die's flip chip bumps are pushed through the underfill material until the flip chip bumps make contact with corresponding package substrate bumps.
FIG. 1
shows a cross-section of a die and package in a conventional no flow underfill process. Flip chip die
110
contains a plurality of flip chip bumps on a surface
112
, one of which is shown as bump
115
. The die
110
is mated to package substrate
120
, which contains substrate bump
130
on substrate bump pad
125
. A layer of solder resist
140
and a layer of filled underfill
135
cover substrate
120
. Die
110
is joined to substrate
120
by pressing flip chip bump
115
through underfill
135
until flip chip bump
115
makes contact with substrate bump
130
. This process can also occur at the wafer level, where the wafer contains a plurality of dies
110
each having a plurality of flip chip bumps
115
. Package substrate
120
would then be part of a panel or sheet containing many substrate pads
125
and bumps
130
configured to mate with the flip chip bumps
115
on the wafer.
Such a no flow process normally results in high open fails, because filler particles are trapped between the flip chip bumps
115
and the substrate bumps
130
. Reducing or eliminating filler in the underfill used in the no flow underfill process is a poor solution to this problem, because doing so restores the problem of poor reliability of the resulting products due to CTE mismatch.
There is therefore a need for an improved process for applying underfill in making IC assemblies.
REFERENCES:
patent: 5136365 (1992-08-01), Pennisi et al.
patent: 5925930 (1999-07-01), Farnworth et al.
patent: 6121689 (2000-09-01), Capote et al.
patent: 6234379 (2001-05-01), Donges
patent: 6238948 (2001-05-01), Ramalingam
patent: 6265776 (2001-07-01), Gilleo
patent: 6316286 (2001-11-01), Trezza
patent: 6335571 (2002-01-01), Capote et al.
patent: 6337265 (2002-01-01), Trezza et al.
patent: 6518677 (2003-02-01), Capote et al.
patent: 6639321 (2003-10-01), Nagarajan et al.
patent: 2001/0051392 (2001-12-01), Akram
Li, Haiying, et al., “Development of New No-Flow Underfill Materials for Both Eutectic Solder and a High Temperature Melting Lead-Free Solder,”2001 Electronic Components and Technology Conference, IEEE, 6 pages.*
Moon, Kyoung-sik, et al., “Study on the Effect of Toughening of No-Flow Underfill on Fillet Cracking,”2001 Electronic Components and Technology Conference, IEEE, 6 pages.*
Morganelli, Paul, Ph.D., et al., “Viscosity of a No-Flow Underfill during Reflow and Its Relationship to Solder Wetting,”2001 Electronic Components and Technology Conference, IEEE, 4 pages.*
Shi, S.H., et al., “Study of the Fluxing Agent Effects on the Properties of No-Flow Underfill Materials for Flip-Chip Applications,”1998 Electronic Components and Technology Conference, IEEE, pp. 117-124.*
Zhang, Zhuqing, et al., “A Novel Approach for Incorporating Silica Filler into No-Flow Underfill,”2001 Electronic Components and Technology Conference, IEEE, 7 pages.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Dilinh
Pham Long
LandOfFree
Flip-chip device with multi-layered underfill having graded... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip-chip device with multi-layered underfill having graded..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-chip device with multi-layered underfill having graded... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3290521