Flip-chip bumping structure with dedicated test pads on...

Details Flip-chip bumping structure with dedicated test pads on... Flip-chip bumping structure with dedicated test pads on...

2000-12-05

2002-03-19

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S048000, C257S778000, C438S666000, C438S108000

Reexamination Certificate

active

06359342

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated-circuit packaging technology, and more particularly, to a flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same.
2. Description of Related Art
Flip-chip technology is an advanced type of integrated-circuit packaging technology which is characterized by that the packaged semiconductor chip is mounted in an upside-down manner over the substrate and bonded to the same by means of solder bumps. Since no bonding wires are required, it allows the overall package size to be made very compact. The attachment of solder bumps to the semiconductor chip is implemented through the so-called bumping process. A conventional flip-chip bumping structure on semiconductor chip is illustratively depicted in the following with reference to FIG.
1
and
FIGS. 2A-2D
.
FIG. 1
shows a schematic top view of a semiconductor chip
10
used for flip-chip application; and
FIGS. 2A-2D
are schematic cross-sectional diagrams used to depict the fabrication of a conventional flip-chip bumping structure over the semiconductor chip
10
of
FIG. 1
(the cross-sectional view of the semiconductor chip
10
is cutting through the line A-A′ in FIG.
1
).
Referring to
FIG. 1
together with
FIG. 2A
, the semiconductor chip
10
is predefined with a lined array of I/O points
11
for the internal circuitry thereof to communicate with external circuitry; and a plurality of metallization pads
20
, which are typically made of aluminum (Al), are formed respectively over the I/O points
11
. Conventionally, these metallization pads
20
serve both as test pads and bump pads.
Referring further to
FIG. 2B
, during testing procedure, a test circuit card (not shown) with a set of probing needles
30
(only one is shown in
FIG. 2B
) is used to check whether the internal circuitry of the semiconductor chip
10
would function properly. Each probing needle
30
is set to come in touch with the exposed surface of each metallization pad
20
for the purpose of establishing an electrical coupling between the test circuit card (not shown) and the internal circuitry of the semiconductor chip
10
via the I/O points
11
. Typically, the testing procedure would be repeatedly performed for several times.
Referring further to
FIG. 2C
, as a consequence of the probing needle
30
repeatedly pressing on the metallization pad
20
, it would undesirably leave some scratches
20
a
over the exposed surface of the metallization pad
20
.
Referring further to
FIG. 2D
, in the next step, a bumping process is performed to form a solder bump
40
on each metallization pad
20
over the semiconductor chip
10
. This completes the fabrication of a flip-chip bumping structure over the semiconductor chip
10
, which can be subsequently used to bond the semiconductor chip
10
to a substrate (not shown).
However, due to the existence of scratches
20
a
over the exposed surface of the metallization pad
20
, the bumping would be undesirably degraded in quality and reliability.
One solution to this problem is to repeat the testing procedure as fewer times as possible, so as to reduce the scratching of the metallization pads
20
to a lesser degree. One drawback to this solution, however, is that it would make the semiconductor chip
10
less assured in reliability.
Moreover, since the metallization pads
20
are spaced at very small intervals, the pitch of the probing needles
30
should be correspondingly small, which would make the testing procedure difficult to realize.
Related patents, include, for example, the U.S. Pat. No. 5,719,449 entitled “FLIP-CHIP INTEGRATED CIRCUIT WITH IMPROVED TESTABILITY”. This patented technology discloses an integrated circuit that is adapted for implementing flip-chip technology with solder bumps, while providing for improved testability.
One drawback to the foregoing patented technology, however, is that, since the dedicated test pads are located on the edge of the chip surface, it would undesirably require the fabrication of additional electrically-conductive paths for electrically connecting the test pads to their corresponding I/O points. This requirement would make the overall packaging process more complex and thus more costly to implement.
SUMMARY OF THE INVENTION
It is an objective of this invention to provide a new flip-chip bumping technology, which can help allow the integrated-circuit testing procedure to be repeated as many times as desired without causing scratches over the bump pads.
It is another objective of this invention to provide a new flip-chip bumping technology, which can help assure the quality and reliability of the attachment of solder bumps over the bump pads.
It is still another objective of this invention to provide a new flip-chip bumping technology, which can help allow an increase in the pitch of the probing needles being used to implement the integrated-circuit testing procedure so as to allow the testing procedure to be carried out in an easier manner.
It is yet another objective of this invention to provide a new flip-chip bumping technology, which can be implemented without having to fabricate additional electrical connecting paths as in the case of the prior art of U.S. Pat. No. 5,719,449.
In accordance with the foregoing and other objectives, the invention proposes a new flip-chip bumping technology.
In terms of method, the flip-chip bumping technology according to the invention comprises the following method steps: (1) forming a plurality of electrically-conductive dual-pad blocks respectively over the I/O points of the semiconductor chip, each dual-pad block including: (i) a first pad, and (ii) a second pad located beside and electrically connected to the first pad; (2) designating the respective first and second pads of the dual-pad blocks alternately as bump pads and test pads; and (3) performing a testing procedure to the internal circuitry of the semiconductor chip by probing through the test-pad portions of the dual-pad blocks. Further, a plurality of solder bumps are formed respectively over the bump-pad portions of the dual-pad blocks.
In terms of structure, the flip-chip bumping technology according to the invention comprises the following components: (a) a lined array of electrically-conductive dual-pad blocks formed over the semiconductor chip and respectively electrically connected to the I/O points of the semiconductor chip, each dual-pad block including: (a1) a first pad, and (a2) a second pad located beside and electrically connected to the first pad; wherein the respective first and second pads of the dual-pad blocks are alternately designated as bump pads and test pads; and (b) a plurality of solder bumps respectively formed over the bump-pad portions of the dual-pad blocks.


REFERENCES:
patent: 4951098 (1990-08-01), Albergo et al.
patent: 5239191 (1993-08-01), Sakumoto et al.
patent: 5446310 (1995-08-01), Baliga et al.
patent: 5473196 (1995-12-01), De Givry
patent: 5719449 (1998-02-01), Struas
patent: 5923047 (1999-07-01), Chia et al.
patent: 5936260 (1999-08-01), Corbett et al.
patent: 6034426 (2000-03-01), Patel et al.

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