Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-23
2001-05-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S614000
Reexamination Certificate
active
06232212
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to electronic assembly technology and more specifically to solder bump interconnections for mounting IC chips and the like on interconnection substrates like silicon, ceramic, or printed circuit boards.
BACKGROUND OF THE INVENTION
Solder bump interconnection techniques for both electrically contacting component packages and mounting them on interconnection substrates such as printed circuit boards have become widely used in the manufacture of electronic devices. The term interconnection substrates includes several forms of electronic device supports including, e.g., silicon and ceramic. For convenience reference to such supports herein will be to printed wiring boards as a generic term.
State of the art component packages are small and lightweight and can be surface mounted to printed circuit boards using fine patterns of solder bumps. Typically, bumps or pads are formed on the printed wiring board and the component package in mirror arrays that mate when the component package is properly placed. Assembly is completed by applying heat to melt the solder and form the solder bond and interconnection. This technique is used in flip-chip technology where the surface of the IC chip in the component package is provided with bonding pads or bumps and the chip is mounted upside down on the printed wiring board.
The solder bumps are formed on arrays of I/O contact pads prior to assembly. To facilitate localized or selective application of solder to the array of contact pads the surface of the pads should be solder wettable. Accordingly, the bonding sites on the components being joined are first provided with under bump metallization (UBM). The solder, typically a tin based solder, e.g. tin-lead, tin-antimony, is then applied to the UBM.
There is a growing choice of methods for applying solder bumps to IC chips and interconnection substrates. The most common, is to print a pattern of solder paste through a screen or stencil, then remove the stencil and reflow the solder. In a similar approach, which eliminates the paste, solder is evaporated through a shadow mask onto the UBM. In both cases, reliability problems increase as the features in the stencil or mask are shrunk to meet demands for ever smaller interconnection pitch. Stencil and shadow mask techniques are, in general, limited to applications in which bump pitch is of the order of 200 &mgr;m or more.
Finer patterns can be produced using thick photoresist patterns and evaporating solder onto the pattern, then removing the unwanted portions using lift-off. However, evaporation of uniform layers on large substrates or boards requires costly equipment and, moreover, is generally limited to high lead solder compositions in order to achieve reasonable evaporation rates.
Solder bumps can also be applied in fine pitch arrays using electrolytic or electroless solder plating. Both techniques use photolithography to define the solder bumps and precisely placed, fine line, bump patterns can be produced. However, use of electrolytic and electroless processes raise other reliability issues. They require very clean processing environments and ultra-clean, electrically active, substrate surfaces, adding cost and complexity to the process.
A recent proposal for solder bump application combines the fine features and precision of photolithography, with the simplicity of solder paste techniques. After forming the UBM, which defines the bump sites, the substrate is coated with a thick layer of photoresist. The bump pattern is then exposed and developed in the photoresist leaving a thick patterned mask. The openings in the photoresist mask are made larger than the desired bump size to provide sufficient solder volume from the solder paste for the final bump. The solder paste is applied in the conventional manner to the openings in the photoresist mask. The solder paste is heated to reflow, and the solder bump self aligns to the only available wettable surface, the UBM. The photoresist is then removed. The risk of excessive solder flow and bridging is avoided because the photoresist mask, which isolates each bump site, remains in place during reflow. Using this technique, solder bump pitch patterns of less than 200 &mgr;m can be produced with high reliability. However, a drawback to this technique is that removal of the photoresist mask after the solder bumps have been formed has proven difficult. This is due to thermally induced crosslinking of the photoresist during the reflow step. It is especially the case when high melting point solders are used. It is well known that prepolymer materials crosslink under the influence of both heat and light. In photolithography, the prepolymer materials are chosen so that a given level of crosslinking will occur under actinic exposure. This level is enough to make the exposed material sufficiently robust to function as a photomask, but still allow it to be easily removed later in processing. If crosslinking exceeds the design level for the photoresist material, removal can be difficult. Photoresist materials are known to form tenacious coatings if subjected to thermal treatments more severe than those for which the material is designed. Accordingly, it can be expected that a photoresist mask, when left in place during a solder reflow step, will tend to crosslink excessively and resist removal. Moreover, in a typical application, the IC chip to which the solder bumps are applied is coated with a capping layer, usually a polyimide. The photoresist polymer, on heating, will stick to the polyimide and may even crosslink to it. Removal of the photoresist, without attacking the IC capping layer, is problematic. Wet solvents are, in many cases, inadequate. Dry etching, i.e. ashing, of the photoresist is more effective but there is little dry etch selectivity between the developed and hardened photoresist, and the capping layer. The same issue arises when this solder bump process is applied to epoxy-glass interconnection substrates.
SUMMARY OF THE INVENTION
A technique has been developed for overcoming the problem of photoresist process incompatibility in the solder bump process described above. According to this technique a buffer layer is interposed between the IC or interconnection substrate, and the photoresist layer. The buffer layer is preferably a thin layer of metal that prevents adhesion of the photoresist to underlying surfaces. The buffer layer can be easily deposited and easily removed. It protects the underlying layers and allows effective techniques, e.g. plasma etching, to be employed to remove the photoresist. In the preferred embodiments, the steps for forming the buffer layer are integrated with forming the UBM.
REFERENCES:
patent: 5137845 (1992-08-01), Lochon et al.
patent: 5767010 (1998-06-01), Mis et al.
patent: 5885891 (1999-03-01), Miyata et al.
patent: 5937320 (1999-08-01), Andricacos et al.
Degani Yinon
Kossives Dean Paul
Lucent Technologies
Nelms David
Thomas Kayden Horstemeyer & Risley LLP
Vu David
Wilde Peter V. D.
LandOfFree
Flip chip bump bonding does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip chip bump bonding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip chip bump bonding will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2557255