Flip-chip bump arrangement for decreasing impedance

Details Flip-chip bump arrangement for decreasing impedance Flip-chip bump arrangement for decreasing impedance

2002-02-04

2004-01-20

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S773000, C257S776000

Reexamination Certificate

active

06680544

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a package technique for an integrated circuit chip, especially relates to the bump arrangement for a flip-chip so as to decrease conductive trace impedance and improve the transferring quality of high frequency signals.
BACKGROUND OF THE INVENTION
With the alternation of the fabricating technology generation for integrated circuits (IC), a single chip having multi-functions are common. A single chip is thus having high integrity of devices. Consequently, the advance of the package techniques to adapt the IC development becomes a trend. The conductive wire used to connect between lead frame and bonding pad of the chip appeared to be poor for a chip of VLSI type, not to mention for ULSI.
It is because the package method of using wires stitched to the bonding pads requires to be improving. In the case of wire boding chip, the bonding pads have to form at the border region of a chip so as to prevent the gold wires from shifting due to wires too long or inject the resin into mold. As a consequence, the longer conductive trace to connect between devices and bonding pads cannot be evaded. In addition, with the functions prompted and the prevalence of the performance of high speed, the number of I/O terminals is increased significantly. The conventional fashion of wires stitch to bonding pads associated with high inductance impedance is no longer suitable for the requirements of the chip merits with high performance IC for nowadays and future's.
Therefore, a package technique for IC chip called flip-chip is developed in accordance with the need described above. The technique, please refer to
FIG. 1
, a conductive bumps
24
array on the top-layer of the chip
20
is shown. The conductive bumps
24
, are not limited to form in the surrounding of the device region of the chip, but are distributed on the chip
20
evenly by an array form. The chip
20
is then flipped to make the chip face down so that the conductive bump array
24
connected to the corresponding pads
28
on the substrate
26
which has corresponding conductive pads (or called flip-chip bump pad)
28
.
For a chip designed as a flip-chip or as a wire-bonding chip type, the bumps in the core region are almost indifference. For a wire-bonding chip, a passivation layer formed atop chip except the bonding pads, which are distributed in the border of the chip. The devices would not be formed at a substrate region right below the bonding pads. For a flip-chip, a conductive trace layer as a redistribution layer is formed on the passivation layer through the steps of metal deposition, lithography and etching steps. The conductive traces of the redistribution layer connect between the bonding pads in surrounding of the chip and the bump in the chip core. Therefore, for IC designed houses are concerned, the currently design tools for the wire bonding chip could be used for a flip-chip designation.
FIG. 2
shows a conventional cross-sectional view of a flip-chip. The elementary structure containing from the bottom to the top are: a poly-silicon layer (a device gate or a conductive layer)
40
, a first inter-level dielectric layer
50
A, a first inter-level conductive layer
60
A, a second inter-level dielectric layer
50
B, a second inter-level conductive layer
60
B, a third inter-level dielectric layer
50
C, a third inter-level conductive layer
60
C, and a passivation layer
70
. The contact
55
A and the vias
55
B and
55
C are, respectively, used to connect in between the polycrystalline silicon layer
40
and the first
60
A, the first
60
A and the second
60
B, the second
60
B and the third inter-level conductive layers
60
C. Atop the passivation layer
70
has a fourth conductive layer, which serves as redistribution layer for the connections in between boding pads and the predetermined bumps position at the chip core. The bumps are then formed through screen-printing to bond bump
95
or through a method of electroplating which are used to deposit the solder bumps
95
on the patterned passivation film
92
.
The conductive bumps aforementioned are all arranged as array type. Furthermore, no matter conductive bumps are of signal or of connecting ground or of source-voltage type, the arrangement is in mixing in each columns and rows. The length of each conductive trace for signal connection may be longer or shorter, all determined by the distances in between bonding pads originally designed for wire bonding chip and the conductive bumps of chip core.
FIG. 3
shows a synoptic top view, which shows the power pad p at surrounding region of the chip connecting to the bump
98
at the core region by a conductive trace of the RDL layer
97
. The ground pad g and the signal pad s at surrounding region of the chip are being connected to the ground bump G or signal bump S through trace
97
. Thus the inductance due to the bended conductive trace and the traces in between are significantly.
The object of the present invention is thus proposed an arrangement for signal bump so that the impedance of the conductive trace can be decreased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a bump arrangement so as to reduce the impedance of conductive traces for signal bump connections.
A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps of surrounding the conductive bumps array, a second ring of conductive bumps surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps arrangement in the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The conductive bumps of the first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer, which has conductive traces and wherein the redistribution layer are at a position in between a passivation layer and the interconnection layer.


REFERENCES:
patent: 5719449 (1998-02-01), Strauss
patent: 6037677 (2000-03-01), Gottschall et al.
patent: 6225143 (2001-05-01), Rao et al.

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