Flattening process for epitaxial semiconductor wafers

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth from gaseous state combined with subsequent...

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438478, 438504, 438974, H01L 2120

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active

060308877

ABSTRACT:
Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 .mu.ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, T.sub.t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T.sub.t.

REFERENCES:
patent: 4877479 (1989-10-01), McNeil et al.
patent: 5238532 (1993-08-01), Zarowin et al.
patent: 5254830 (1993-10-01), Zarowin et al.
patent: 5290382 (1994-03-01), Zarowin et al.
patent: 5291415 (1994-03-01), Zarowin et al.
patent: 5292400 (1994-03-01), Mumola
patent: 5372674 (1994-12-01), Steinberg
patent: 5375064 (1994-12-01), Bollinger
patent: 5376224 (1994-12-01), Zarowin
patent: 5419803 (1995-05-01), Mumola
patent: 5449638 (1995-09-01), Hong et al.
patent: 5474647 (1995-12-01), Poultney et al.
patent: 5491571 (1996-02-01), Williams et al.
patent: 5543919 (1996-08-01), Mumola
patent: 5563709 (1996-10-01), Poultney
G. Pfeiffer, "Final Polish For SOI Wafters-Surface Roughness and TTV Degradation", Proceedings 1995 IEEE International SOI Conference, pp. 172-173, 1995.
Aug. 17, 1998 PCT International Search Report (PCT/US98/06531).
F. Shimura, "Semiconductor Silicon Crystal Technology", Academic Press, pp. 191-195, 1989.

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