Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-04-15
2003-09-09
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S164000
Reexamination Certificate
active
06617203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flat panel display device and a method of manufacturing the same, and, more particularly, to a flat panel display device manufactured according to a method using fewer masks and resulting in high brightness and simplified manufacturing.
2. Description of Related Art
In general, a flat panel display device includes a display panel and a driving circuit that drives the display panel. The display panel and the driving circuit are manufactured through different processes and then attached to each other. Thus, there is a problem in that the manufacturing process for each component is complicated, and the production cost for each is high.
In efforts to solve the problem, a technique is developed so that pixels and driving integrated circuits (ICs) are formed on a single substrate in such a way that the pixel is arranged on a display region of the substrate, and the driving ICs are arranged on a non-display region of the substrate. For example, in the case of an organic Electroluminescent (EL) display device, two thin film transistors (TFTs), a storage capacitor and an organic EL element are formed on the display region, and a CMOS transistor as a driving circuit element is formed on the non-display region.
FIG. 1
is a cross-sectional view illustrating a conventional flat panel display device having a CMOS transistor as a driving circuit element. A method of manufacturing the conventional flat panel display device is provided below with reference to FIG.
1
.
First, a transparent insulating substrate
10
having a display region
11
and a non-display region
15
is provided. The display region
11
includes a first display region
12
on which a TFT used to drive the pixels is formed, and further includes a second display region
13
on which an organic EL element is formed. The non-display region
15
includes a first non-display region
16
on which an NMOS TFT is formed, and further includes a second non-display region
17
on which a PMOS TFT is formed.
A buffer layer is formed on the transparent insulating substrate
10
. Then, first to third semiconductor layers
21
to
23
are formed on the buffer layer of the transparent insulating substrate
10
using a first mask. The first semiconductor layer
21
is arranged over the first non-display region
16
, and the second semiconductor layer
22
is arranged over the second non-display region
17
. The third semiconductor layer
23
is arranged over the first display region
12
.
A gate insulating layer
40
is formed over the entire surface of the transparent insulating substrate
10
. First to third gate electrodes
41
to
43
are formed on the gate insulating layer
40
using a second mask. The first gate electrode
41
is arranged over the first semiconductor layer
21
, and the second gate electrode
42
is arranged over the second semiconductor layer
22
. The third gate electrode
43
is arranged over the third semiconductor layer
22
.
Using the first gate electrode
41
as a mask, an n-type low-density impurity is ion-implanted into the first semiconductor layer
21
to form first low-density source and drain regions
37
and
38
.
Using a third mask, an n-type high-density impurity is ion-implanted into the first semiconductor layer
21
to form first high-density source and drain regions
31
and
32
.
Hence, the first semiconductor layer
21
has a lightly doped drain (LDD) structure. However, when an ion-implanting process (used to form the first low-density source and drain regions
37
and
38
) is omitted, the first semiconductor layer
21
has an offset structure.
Using a fourth mask that exposes the remaining portion except for the first non-display region
16
, a p-type high-density impurity is ion-implanted into the second and the third semiconductor layers
22
and
23
to form second source and drain regions
33
and
34
and third source and drain regions
35
and
36
, respectively.
At this point, the third source and drain regions
35
and
36
are formed by ion-implanting a p-type impurity so as to form a PMOS TFT as a TFT for driving pixels. However, in order to form an NMOS TFT as a TFT for driving pixels, during a third mask process, an n-type high-density impurity can be ion-implanted into the third semiconductor layer
23
.
Subsequently, an interlayer insulating layer
50
is formed over the entire surface of the transparent insulating substrate
10
. Then, using a fifth mask, the gate insulating layer
40
and the interlayer insulating layer
50
are simultaneously etched to form contact holes
51
to
56
.
Thereafter, using a sixth mask, first to third source and drain electrodes
61
to
66
are formed. The first to the third source and drain electrodes
61
to
66
are electrically connected to the first to third source and drain regions
31
to
36
through the contact holes
51
to
56
, respectively.
A passivation layer
70
is formed over the entire surface of the transparent insulating substrate
10
. Using a seventh mask, the passivation layer
70
is etched to form via hole
71
. The via hole
71
exposes a portion of either of the third source and drain electrodes
65
and
66
. In
FIG. 1
, the via hole
71
exposes the third drain electrode
66
.
Using an eighth mask, a pixel electrode
80
is formed over the second display region
13
. The pixel electrode
80
serves as a lower electrode of the organic EL element and is made of a transparent conductive material. The pixel electrode
80
is also electrically connected to the third drain electrode
66
through the via hole
71
.
A planarization layer
90
is formed over the entire surface of the transparent insulating substrate
10
and etched using a ninth mask to form an opening portion
91
that exposes a portion of the pixel electrode
80
.
Even though not shown in
FIG. 1
, an organic EL layer is formed on the pixel electrode
80
to cover the opening portion
91
. Also, an upper electrode is formed to cover the organic EL layer. Therefore, the conventional flat panel display device is completed.
However, since nine masks are required to manufacture the conventional flat panel display device as described above, the manufacturing process is quite complicated, thereby lowering a manufacturing yield. In addition, light emitting from the organic EL layer formed on the pixel electrode
80
has to pass through several layers, including the gate insulating layer
40
, the interlayer insulating layer
50
, and the passivation layer
70
. Hence, most of the light emitting from the organic EL layer is lost due to multi-reflection. As a result, light transmittance is lowered as is the brightness of the panel.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a flat panel display device having a simplified manufacturing process.
It is another object of the present invention to provide a flat panel display device having a high brightness.
In order to achieve the above objects, the preferred embodiments of the present invention provide a method of manufacturing a flat panel display device including at least first to fourth TFTs, the first, the third, and the fourth TFTs having a first conductive type, the second TFT having a second conductive type. The method disclosed comprising: a) providing a substrate having a non-display region on which the first and second TFTs are formed, and a display region on which the third and fourth TFTs are formed; b) forming first to fourth semiconductor layers of the first to the fourth TFTs on the substrate; c) forming a gate insulating layer over the entire surface of the substrate; d) forming first to fourth conductive patterns and a pixel electrode on the gate insulating layer, such that the first to the fourth conductive patterns are formed over the first to the fourth semiconductor layers, and the pixel electrode is formed over a portion of the display region; e) forming first to fourth gate electrodes and a fifth conductive pattern, such that th
Kim Chang-Soo
Lee Sang-Won
Jr. Carl Whitehead
McGuireWoods LLP
Samsung SDI & Co., Ltd.
Schillinger Laura W
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