Flash with consistent latency for read operations

Static information storage and retrieval – Read/write circuit – Multiplexing

Reexamination Certificate

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Details

C365S189040, C365S189120, C365S194000

Reexamination Certificate

active

11005939

ABSTRACT:
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires a predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.

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