Flash step preparatory to dielectric etch

Details Flash step preparatory to dielectric etch Flash step preparatory to dielectric etch

2002-06-05

2004-09-07

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S712000, C438S714000, C438S717000, C438S723000, C438S724000

Reexamination Certificate

active

06787475

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to plasma etching in integrated circuit fabrication. In particular, the invention relates to a cleaning step performed prior to a dielectric etch step.
2. Background Art
Modern integrated circuits contain many levels of metallization, each including a dielectric layer separating one level of horizontal wiring from another. As illustrated in the cross-sectional view of
FIG. 1
, a lower layer
10
includes conductive features
12
at its surface needing to be electrically contacted from above. The lower layer
10
may be a dielectric layer in which the conductive features
12
are metal features, or it may be the silicon substrate in which the conductive features are doped regions of the silicon forming part of an active device. In order to increase the number of active devices and allow for complex wiring, the conductive features
12
have small lateral size and are packed closely together. An inter-level dielectric layer
14
is deposited on the lower layer
10
. The dielectric layer
14
is typically formed of a silicon oxide deposited in a plasma CVD process using TEOS as a precursor, but more advanced dielectrics with low dielectric constants are being developed. The inter-level dielectric layer
14
typically has a thickness of about 1 &mgr;m. The photolithography required for etching the contact and via holes through the dielectric often requires that the dielectric layer
14
be covered by a thin anti-reflective coating
16
, commonly referred to as ARC. It maybe composed of BARC, a silicon-containing organic material, and have a thickness of 50 to 80 nm. However, inorganic ARCs, for example, of silicon nitride, are also well known. A photoresist layer
18
is deposited over the anti-reflective coating
16
and is photographically patterned to form mask holes
20
,
22
. The smaller mask holes
20
correspond to the width and location of to via or contact holes to be etched in the dielectric layer
14
to contact the conductive features
12
. The anti-reflective coating
16
has a thickness and refractive index that are selected to minimize extraneous scattering of the patterning light, which would degrade the resolution of the photolithography of the smaller mask holes
20
. This description of the dielectric layer
14
is overly simplified. It may further include an etch stop layer at its bottom, and in complex interconnect schemes like dual damascene another etch stop layer vertically separates two parts of the dielectric.
After the photomask has been defined, the wafer is placed into a plasma etch reactor to etch contact or via holes
24
, illustrated in the cross-sectional view of
FIG. 2
, through openings in the anti-reflective layer
16
and the dielectric layer
14
to expose the underlying conductive features
12
. Either a contact hole or a via hole may be referred to as a plug hole. The contact or via holes
20
are then filled with a metal, such as aluminum, copper, or tungsten, to provide a vertical electrical connection through the dielectric layer
14
to contact the lower conductive features
12
to a horizontal electrical arrangement defined above the dielectric layer
14
. This process may be repeated five times or more for advanced integrated circuits having multiple levels of metallization.
For advanced devices, the contact or via holes
24
are typically rectangular or square having a minimum width for advanced devices of 0.25 &mgr;m or smaller and requiring a highly anisotropic etch to produce holes having a high-aspect ratio.
The larger mask hole
22
in the photoresist layer
18
defines through the dielectric layer
14
one or more open pads
26
. The larger mask hole
22
is etched at the same time as the contact or via holes
24
, according to the same etching process. The open pad
26
, which can alternatively be called a monitoring area, is also typically rectangular or square and has significantly larger lateral dimensions than do the contact or via holes
20
, by, for example, a factor of at least 50. A lateral dimension of 20 &mgr;m is typical. The open pad
26
is usually located in an area of the chip or wafer not associated with the active devices and does not form a functional part of the integrated circuit being fabricated. It is called an open pad because it resembles a pad used for electrically contacting a bonding wire or other external electrical contact to the integrated circuit, but an open pad is never used as a contact. Indeed, open pads are typically formed in each level of metallization to monitor deposition and etching conditions for each level.
Because of its large size, the open pad
26
is more easily imaged than the very small contact and via holes. For example, etch rate and residues can be optically imaged in the open pad
26
while corresponding measurements in the narrow contact and via holes
24
typically require destructive sectioning of the wafer and time consuming electron microscopy. While open pads are particularly useful in developmental work, they also are frequently used in a production environment to assure that the standardized etch rates are being maintained.
Microloading effects are well known in which the aspect ratio of holes being etched and even the density of high aspect-ratio holes influence the etching rate. While microloading complicates the correspondence between etching rates of the narrow contact and via holes and of the much wider open pads, as long as the differences are small and fixed, a usable correlation can be obtained by applying empirically obtained proportionality factors.
Etching of the closely spaced, high aspect-ratio contact and via holes in the oxide dielectric requires an anisotropic etch. Further, the oxide etch should be highly selective to both photoresist and to silicon nitride etch stop layers defining the end of the etching profile. Such requirements have necessitated refinements in etching processes and plasma reactors. A particularly successful oxide chemistry is based on hexafluorobutadiene (C
4
F
6
), a hydrogen-free fluorocarbon that has a low F/C ratio of 1.5. Octafluorocyclopentene (C
5
F
8
) has a somewhat higher F/C ratio of 1.6 but still offers many of the same advantages. Octafluorocyclobutane (C
4
F
8
) is commonly used in the industry, but its F/C ratio of 2.0 is disadvantageously high for etching vias with very high aspect ratios. During a plasma etch performed under the correct conditions, the fluorocarbon forms a protective polymer on the vertical sidewalls and on bottom non-oxide surfaces of the hole being etched. Thereby, the etch can form vertical sidewalls and be selective to underlying silicon or silicon nitride.
In U.S. patent application Ser. No. 09/522,374, filed Mar. 10, 2000, now issued as U.S. Pat. No. 6,451,703, and incorporated herein by reference in its entirety, Liu et al. describe plasma oxide etch of oxide performed in the magnetically enhanced reactive ion etch (MERIB) reactor
30
schematically illustrated in FIG.
3
. Such a reactor is the eMax reactor commercially available from Applied Materials of Santa Clara, California. It includes a grounded vacuum chamber
32
, perhaps including liners to protect the walls. A wafer
34
is inserted into the chamber
32
through a slit valve opening
36
and placed on a cathode pedestal
38
with an electrostatic chuck
40
selectively clamping the wafer. The chuck powering is not illustrated. Unillustrated fluid cooling channels through the pedestal
38
maintain the pedestal at reduced temperatures. A thermal transfer gas such as helium is supplied to unillustrated grooves in the upper surface of the pedestal
38
facing the back side of the wafer
34
. The thermal transfer gas increases the efficiency of thermal coupling between the temperature controlled pedestal
38
and the wafer
34
, which is held against the pedestal
38
by the electrostatic chuck
40
or an alternatively used peripheral wafer clamp.
An RF power supply
42
, preferably operating at 13.56 MHz, is connected to the cathode pedestal
38

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