Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-15
2003-11-25
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000, C438S636000, C438S761000
Reexamination Certificate
active
06653190
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to semiconductor technology and more specifically to controlling wordline width in MirrorBit® Flash memory.
2. Background Art
Various types of memories have been developed in the past as electronic memory media for computers and similar systems. Such memories include electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM). Each type of memory had advantages and disadvantages. EEPROM can be easily erased without extra exterior equipment but with reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lack erasability.
A newer type of memory called “Flash” EEPROM, or Flash memory, has become extremely popular because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power. It is used in many portable electronic products, such as cell phone, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
In Flash memory, bits of information are programmed individually as in the older types of memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips. However, in DRAMs and SRAMs where individual bits can be erased one at a time, Flash memory must currently be erased in fixed multi-bit blocks or sectors.
Conventionally, Flash memory is constructed of many Flash memory cells where a single bit is stored in each memory cell and the cells are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. However, increased market demand has driven the development of Flash memory cells to increase both the speed and the density. Newer Flash memory cells have been developed that allow more than a single bit to be stored in each cell.
One memory cell structure involves the storage of more than one level of charge to be stored in a memory cell with each level representative of a bit. This structure is referred to as a multi-level storage (MLS) architecture. Unfortunately, this structure inherently requires a great deal of precision in both programming and reading the differences in the levels to be able to distinguish the bits. If a memory cell using the MLS architecture is overcharged, even by a small amount, the only way to correct the bit error would be to erase the memory cell and totally reprogram the memory cell. The need in the MLS architecture to precisely control the amount of charge in a memory cell while programming also makes the technology slower and the data less reliable. It also takes longer to access or “read” precise amounts of charge.
Thus, both speed and reliability are sacrificed in order to improve memory cell density.
An even newer technology allowing multiple bits to be stored in a single cell is known as “MirrorBit®” Flash memory has been developed. In this technology, a memory cell is essentially split into two identical (mirrored) parts, each of which is formulated for storing one of two independent bits. Each MirrorBit Flash memory cell, like a traditional Flash cell, has a gate with a source and a drain. However, unlike a traditional Flash cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, each MirrorBit Flash memory cell can have the connections of the source and drain reversed during operation to permit the storing of two bits.
The MirrorBit Flash memory cell has a semiconductor substrate with implanted conductive bitlines. A multilayer storage layer, referred to as a “charge-trapping dielectric layer”, is formed over the semiconductor substrate. The charge-trapping dielectric layer can generally be composed of three separate layers: a first insulating layer, a charge-trapping layer, and a second insulating layer. Wordlines are formed over the charge-trapping dielectric layer perpendicular to the bitlines. Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts as a control gate, and changing bitline connections such that one bit is stored by source and drain being connected in one arrangement and a complementary bit is stored by the source and drain being interchanged in another arrangement.
Programming of the cell is accomplished in one direction and reading is accomplished in a direction opposite that in which it is programmed.
A major problem with the MirrorBit architecture has been discovered as the memory cells are scaled down in size or shrunk and the electrical resistance of the cells increases faster than the scale down in size. The relatively higher electrical resistance in smaller devices results in higher power requirements, and subsequent heat generation with reduced life expectancy, for the memory cell.
A solution to this problem has been long sought but has long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a manufacturing method for semiconductor devices, which includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material. With the wordlines of the design widths, the higher electrical resistance in smaller devices is reduced resulting in lower power requirements, and subsequent reduced heat generation with longer life expectancy, for the memory cell. Further, with control over the wordlines widths, the memory cells can be placed closer together resulting in further size reductions for the entire circuitry.
REFERENCES:
patent: 6348406 (2002-02-01), Subramanian et al.
patent: 6365509 (2002-04-01), Subramanian et al.
patent: 6479348 (2002-11-01), Kamal et al.
patent: 6485988 (2002-11-01), Ma et al.
patent: 6492222 (2002-12-01), Xing
Bell Scott A.
Ghandehari Kouros
Hopper Dawn M.
Hui Angela T.
Kamal Tazrien
Advanced Micro Devices , Inc.
Cuneo Kamand
Ishimaru Mikio
Sarkar Asok Kumar
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