Flash memory structure with stacking gate formed using...

Details Flash memory structure with stacking gate formed using... Flash memory structure with stacking gate formed using...

2000-04-28

2001-07-17

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S633000

Reexamination Certificate

active

06261905

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor memory devices in general, and in particular, to the fabrication of a flash memory cell using damascene-like structures.
(2) Description of the Related Art
A conventional memory cell, such as the electrically programmable read-only memory (EPROM) cell, usually comprises a single field effect transistor (FET) having a stacked floating gate and a control gate. A related stacked memory cell is shown in FIG. la, where source/drain regions (
11
) separated by channel area (
15
) are formed in semiconductor substrate (
10
). As is well-known in the art, floating gate (
30
) and control gate (
50
) are typically formed by patterning two conductively doped polysilicon layers, and the floating gate is completely surrounded by an electrically isolating dielectric, hence, its name. However, because the floating gate is formed by etching a first polysilicon layer over a thin gate oxide layer (
20
) grown on channel area (
15
) of the FET, there is usually damage done to the underlying active region of the cell. In addition, there is the problem of poly residue after the etching, which raises reliability issues. It is common practice to use highly selective etch to prevent the residue, but that also has the attendant problems of eroding and distorting the gate geometries which in turn affect the gate coupling ratio. It is disclosed in the embodiments of the present invention a method of forming a stacked gate of a flash memory cell without damaging the active regions, and also with well-defined gate profile. This will be accomplished by applying a modified damascene process to the fabrication of a flash memory cell. As it will be described later, in a damascene process, metal is deposited in a channel that has already been formed in an insulator, rather than depositing the material first on the insulator and defining, or, shaping it later by etching, as is customarily done. In the present invention, gate material, such as polysilicon, and not metal, is deposited into a damascene structure that will have been already formed.
As seen in FIG. la, floating gate (
30
) is separated from the substrate and the control gate by the dielectric layers (
20
) and (
40
), respectively. Control gate (
50
) is formed on the dielectric insulating layer (
40
) aligned over the floating gate, and is accessed by the peripheral circuits on the EPROM chip via word lines that interconnect the FET control gats. The control gate and floating gate are capacitively coupled through the thin dielectric layer.
In an array, the selected cells are coded (programmed) by applying a sufficiently high voltage potential between the control gate and the FET drain, resulting in the injection of hot channel electrons in the substrate through the thin gate oxide into the floating gate. Since the floating gate is well insulated, the accumulated charge is retained for an indefinite period of time thereby providing an array of coded non-volatile memory cells.
The charge stored on the floating gate shifts the threshold voltage, V
t
, on the programmed FET (charged FET), while the V
t
on the uncharged (non-programmed FET) is not shifted in value. When the memory cell on the EPROM chip is selected by the addressed decode circuit on the periphery of the EPROM chip, and a gate voltage V
g
is applied to the control gate having a value between the V
t
of the non-programmed and programmed FETs, the non-programmed FET turns on and the programmed FET does not. The conductive state (on or off) of the FET channel is then interpreted as digital binary ones or zeros.
Typically, the stored data (electrical charge) on the EPROM chip is erased by removing the chip from the equipment, and exposing it for 20 to 30 minutes to ultraviolet radiation to generate electron-hole pairs in the gate oxide and to thereby provide an electrical path to discharge the floating gate. By incorporating these floating gates in a circuit with the proper circuit design, the floating gates can be discharged (erased) by reversing the polarity of the programming voltage, allowing for the fabrication of electrically erasable programmable read-only memory (EEPROMs). And further, by providing for the simultaneous erasure of all the coded memory cells, flash EEPROMs can also be fabricated.
The double gate in the FET patterned from the two doped polysilicon layers represents a capacitive divider. It is desirable to have the threshold voltage V
t
as low as possible for higher density EPROM circuits. Thus, for even an uncharged floating gate, the FET appears to have a higher threshold voltage V
t
as viewed from the control gate than an equivalent FET would have without the floating gate. For example, a gate voltage of V
2
on control gate (
50
) of FIG.
1
a
results in a low voltage V
1
on floating gate (
30
) having a value of V
1
=K×V
2
, where K=C
2
/(C
1
+C
2
) is the capacitive coupling constant, C
2
is the capacitance between the control gate and the floating gate, and C
1
is the capacitance between the floating gate and conducting channel (
15
) of the FET. To minimize the operating and programming voltages, it is desirable to have the capacitive coupling between the control gate and floating gate as large as possible, therefore C
2
should be as large as possible.
Unfortunately, during the further downscaling of the minimum feature sizes on the EPROM integrate circuit to achieve much higher densities required for future EPROM chips having a reasonable size, it is necessary to reduce the area that the memory cell occupies on the chip. However, this necessarily reduces the area of the gate electrodes, and thereby reduces the capacitive coupling ratio K between the floating and control gates on a conventional prior art EPROM. This reduction in area is exacerbated by the conventional methods of forming the stacked gates, namely, by first depositing polysilicon layers and etching them. The etching usually distorts and erodes the shape and size of the intended gates. This problem can be alleviated by applying a modified damascene process as disclosed in the present invention.
The term ‘damascene’ is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, grooves and holes in appropriate locations in the grooves are formed in an insulating material by etching, which are then filled with metal. Metal in grooves form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or grooves, are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, hole openings are also formed at appropriate places in the groove further into the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process, two insulating layers (
120
) and (
130
) are formed on a substrate (
100
) with an intervening etch-stop layer (
125
) as shown in
FIG. 2
a
. A desired trench or groove pattern (
150
) is first etched into the upper insulating material (
130
), as shown in
FIG. 2
a
, using conventional photolithographic methods and photoresist (
140
). The etching stops on etch-stop layer (
125
). Next, a second photoresist layer (
160
) is formed over the substrate, thus filling the groove opening (
150
), and patterned with hole opening (
170
), as shown in
FIG. 2
b
. The hole

Affiliated with

Also associated with

Rating

Flash memory structure with stacking gate formed using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash memory structure with stacking gate formed using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory structure with stacking gate formed using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2554825