Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-11-05
2000-06-06
Thomas, Tom
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438258, 438259, 438266, 438294, 438296, 438524, 438523, 438526, 257314, 257315, H01L 21336
Patent
active
060717769
ABSTRACT:
A method of manufacturing a flash memory structure that also includes the process of forming a shallow trench isolation structure. The method comprises the steps of providing a semiconductor substrate, and then forming a shallow trench isolation structure within the substrate. Thereafter, etching is carried out to form a shallow trench within a portion of the shallow trench isolation structure. The shallow trench is formed where a common source terminal is subsequently formed. Next, metallic material is deposited into the trench to form a buried metallic layer. Then, a stacked gate is formed above the semiconductor substrate. Finally, ions are implanted into the substrate on each side of the stacked gate using the stacked gate itself as a mask to form a source region and a drain region. The source region and the buried metallic layer are connected together to form a common source region. The process of forming the buried metallic layer in the substrate not only is compatible with the process of forming a shallow trench isolation structure, but the device so formed also takes up less chip area. Hence, a device array having a higher density can be produced.
REFERENCES:
patent: 5547884 (1996-08-01), Yamaguchi et al.
patent: 5571736 (1996-11-01), Paterson et al.
patent: 5792694 (1998-08-01), Park
Huang Jiawei
Parekh Nitin
Thomas Tom
United Semiconductor Corp.
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