Flash memory process using polysilicon spacers

Details Flash memory process using polysilicon spacers Flash memory process using polysilicon spacers

1998-06-05

2002-04-02

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S265000, C438S304000, C438S591000, C438S595000

Reexamination Certificate

active

06365455

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor electronic devices and a method for manufacturing the same. More particularly, the present invention relates to a process suited for manufacturing erasable programmable read-only memory cells.
Erasable programmable read-only memory (“EPROM”) technology is known for use in both memory and programmable logic applications. In particular, EPROMs are implemented using floating gate field effect transistors in which the binary states of the EPROM cell are represented by the presence or absence of sufficient charge on the floating gate to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light and are typically referred to as ultraviolet erasable programmable read-only memories (“UVEPROM”s). As seen in
FIG. 1
, a UVEPROM cell
10
typically includes two polysilicon gates disposed above a P-doped substrate
12
having a pair of spaced-apart N-doped active regions
14
and
16
defining a channel region
18
therebetween. The two polysilicon gates are disposed above the channel region
18
with the opposing ends of each of the polysilicon gates overlapping one of the active regions
14
and
16
. One gate is disposed between the remaining gate and the substrate
12
, defining a floating gate
20
. The remaining gate is spaced apart from the floating gate
20
and defines a control gate
22
. The floating gate
20
is embedded in an oxide
24
which facilitates capacitive coupling to both the control gate
22
and the substrate
12
.
A UVEPROM cell is programmed by running a high current between the active regions
14
and
16
while applying a positive potential to the control gate
22
. This is typically achieved by grounding one of the active regions, such as the source
14
, while applying the positive potential to both the control gate
22
and the remaining active region, the drain
16
. In this fashion, electrons in the substrate
12
obtain sufficient energy to overcome the 3.2 eV energy barrier at the interface between the silicon substrate and the silicon dioxide. This phenomenon is typically called electron injection. The positive voltage on the floating gate
20
causes the electrons to collect thereon. The cell
10
is erased by internal photo emission of electrons from the floating gate
20
to the control gate
22
and the substrate
12
. Ultraviolet light increases the energy of the floating gate electron to a level where they jump the 3.2 eV energy barrier and return to the substrate
12
.
Another form of EPROM is the electrically erasable programmable read-only memory (“EEPROM or E
2
PROM”). EEPROMs generally include two serially connected N-channel metal oxide semiconductor transistors in which one of the transistors has an additional gate that is floating and is sandwiched between a control gate and a channel. This floating gate is used to store positive or negative charges which determine the state of the EEPROM. The other transistor is used for selection purposes. The electrons transfer between the floating gate and the drain by Fowler-Nordheim tunneling. This is a quantum mechanical phenomenon that allows electrons to pass through the aforementioned silicon substrate-silicon dioxide interface at an energy below 3.2 eV. Programming of the cell is achieved by tunneling from the floating gate to the drain, leaving the floating gate relatively more positively charged. In the erase mode, the control gate is at a high voltage and the drain is grounded. A drawback with Fowler-Nordheim tunneling is that it often results in over-erasure of the EEPROM cell which tends to leave the floating gate positively charged.
To overcome the over-erasure problem associated with Fowler-Nordheim tunneling, a split gate EPROM cell
26
, shown in
FIG. 2
, was developed. The split gate cell
26
merges the control gate
28
with the floating gate
30
over the channel
32
. The split gate cell
26
is characterized by the control gate
28
having a first conductive region
34
that extends parallel to both the channel
32
and the floating gate
30
and a second region
36
that extends from the first conductive region
34
, transversely thereto toward the channel
32
. The second conductive region
36
prevents the cell from “turning-on” as a result of positive charge on the floating gate
30
. As before, the floating gate is embedded in an oxide layer
38
so as to be capacitively coupled to both the control gate
28
and the channel region
32
.
A problem encountered with the manufacture of EPROMs concerned irregularities in the width of the oxide layer or spacer. Specifically, areas of the oxide layer are formed so that they are relatively thin due to sharp needle-like protrusions that extend from the surface of the polysilicon gate into the thermal oxide. This results from oxidation progressing faster along certain crystal directions. Electric fields concentrate at the tips of these protrusions which support enhanced localized conduction as much as an order of magnitude greater than in protrusion-free silicon surfaces.
Recent trends in EPROM design have employed thermal techniques to control the size and shape of these protrusions. In this fashion, silicon oxide layers having a greater over-all thickness may be employed while still providing Fowler-Nordheim tunneling. However, controlling the size and shape of these protrusions is particularly problematic with the split gate cell design as it may cause shorting between the gates, in a worse case, and can make charge retention in the floating gate problematic. These protrusions may cause premature erasing of the cell in the most harmless case.
What is needed, therefore, is an EPROM cell and method for manufacturing the same, which allows precise control of the thickness of dielectric oxide layers positioned on the floating gate.
SUMMARY OF THE INVENTION
According to the present invention, a technique including a method and structure for a semiconductor integrated circuit device is provided. In an exemplary embodiment, the present invention provides a novel technique for manufacturing sidewall spacers for a flash memory cell. The technique is relatively easy to use and provides a high degree of accuracy.
In a specific embodiment, the present invention provides a method of forming an electrically programmable read-only memory (“EPROM”) cell. The method includes a step of providing a substrate having a dielectric layer thereon (e.g., tunnel oxide, tunnel oxynitride, tunnel nitride), and forming a gate electrode having edges overlying the dielectric layer. The gate electrode can have a nitride cap layer thereon. In most embodiments, the gate electrode and nitride cap layer are made by way of masking and etching processes. The gate electrode can have substantially vertical edges, but is not limited to such vertical edges. A first oxide layer is formed overlying the nitride cap layer and edges of the gate electrode to isolate and insulate the gate electrode. The first oxide layer can be made using a variety of techniques such as thermal or steam oxidation, chemical vapor deposition, and the like. An amorphous silicon layer is formed overlying the oxide layer to a selected thickness. To form amorphous silicon, a chemical vapor deposition technique at low temperature is used. Chemical vapor deposition forms a highly uniform amorphous silicon layer, which has a uniformity ranging from about ±12% about ±15%. The amorphous silicon can be undoped or doped, depending upon the application. In some embodiments, the silicon layer is not amorphous but is polycrystalline silicon, which is highly uniform.
A second oxide layer is formed overlying the amorphous silicon layer by way of, for example, a thermal oxidation technique, but can be others. The present method forms sidewall spacers on the edges of the gate electrode from at least the thickness of the amorphous silicon layer, and in some ca

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