Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-07-09
1999-06-08
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438201, H01L 218247
Patent
active
059111054
ABSTRACT:
A flash memory manufacturing method according to the present invention comprising the steps of: forming a memory cell formation region, one conductivity type MOS transistor formation region and an MOS transistor formation region opposite in conductivity type to the one conductivity type MOS transistor on a semiconductor substrate; forming a polycrystalline silicon layer on an entire surface; selectively forming a resist film on an entirety of the memory cell formation region and part of the polycrystalline silicon layer which corresponds to gate electrodes in the one conductivity type MOS transistor formation region and the opposite conductivity type MOS transistor formation region; selectively etching the polycrystalline silicon film by using the resist film as a mask and forming gate electrodes on the one conductivity type MOS transistor formation region and the opposite conductivity type MOS transistor formation region, respectively; and after the step of forming the gate electrodes, forming a source and drain region in the one conductivity type MOS transistor formation region by injecting one conductivity type impurities by using the resist film as a mask by ion implantation.
REFERENCES:
patent: 5036018 (1991-07-01), Mazzali
patent: 5153143 (1992-10-01), Schlais et al.
patent: 5175120 (1992-12-01), Lee
patent: 5223451 (1993-06-01), Uemura et al.
Japanese Office Action dated Jul. 28, 1998 with English Language translation of Japanese Examiner's comments.
Chaudhari Chandra
NEC Corporation
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