Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2000-06-15
2001-10-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S758000, C438S761000, C438S787000, C438S791000, C257S639000, C257S640000, C257S646000, C257S649000
Reexamination Certificate
active
06306777
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuits and fabrication techniques for forming interpoly dielectric stacks used in flash memory technology. More particularly, the present invention relates to integrated circuits and fabrication techniques for forming “ONO” interpoly dielectric stacks used in flash memory technology. Even more particularly, the present invention relates to integrated circuits and fabrication techniques for improving the structural and electrical integrity, hence the reliability, of the bottom oxide layer of an “ONO” interpoly dielectric stack used in flash memory technology.
BACKGROUND OF THE INVENTION
The current state of the art in flash memory technology uses an interpoly dielectric stack typically consisting of the following layers: silicon dioxide (bottom), silicon nitride (middle), and silicon dioxide (top), known as an “ONO” (hereinafter referred to as ONO). The thickness of the ONO stack ranges from 100 Å to 300 Å, assuming a dielectric constant of 3.7 for the entire dielectric stack. The top oxide layer of the ONO stack is typically formed by thermal growth in an ambient steam. The middle nitride layer of the ONO stack is typically thinned during the formation of the top oxide layer. The bottom oxide layer of the ONO stack is exposed to the conditions arising from the formation of these two upper layers of the ONO stack. Accordingly, the electrical integrity of the bottom oxide layer is extremely critical to device performance. The thinning action acting on the previously formed oxide or nitride layer of the ONO stack introduces a problem: unreliable thickness determination of the completed ONO stack.
While U.S. Pat. Nos. 5,166,904 and 4,758,986 disclose texture asperities and roughness on polysilicon surfaces for the purpose of creating asymmetry in the structure to affect the electron tunneling and the magnitude of the tunneling threshold voltage, to Applicants' knowledge, no known flash memory fabrication process exists for forming nor flash memory structure exists having a specially formed treatment layer as a protective layer disposed between a bottom layer of a multi-layered interpoly dielectric stack prior to formation of the complete interpoly dielectric stack. In addition, no known flash memory fabrication process exists for forming nor flash memory structure exists, having a specially formed treatment layer, described supra, which both optimizes and improves structural and electrical characteristics of the subsequently formed interpoly dielectric stack, notwithstanding any adverse thinning action introduced by the dielectric stack fabrication process. Further, no known flash memory fabrication process exists for forming nor flash memory structure exists, having a specially formed treatment layer, supra, which both improves the reliability of the bottom oxide layer of an ONO interpoly dielectric stack and facilitates decreasing pf an ONO stack thickness, thereby resulting in capacitor coupling ratio changes of the flash memory element and, therefore, allowing the use of new power supply and programming voltages.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a flash memory fabrication processes for forming and producing a flash memory structure having a specially formed treatment layer formed as a protective layer disposed between a bottom layer of a multi-layered interpoly dielectric stack prior to formation of the complete interpoly dielectric stack. The present invention also provides a flash memory fabrication process for forming and producing a flash memory structure having a specially formed treatment layer formed as a protective layer disposed between a bottom oxide layer member of an ONO interpoly dielectric stack that facilitates decreasing of ONO stack thickness, thereby resulting in changes to the capacitor coupling ratio of the flash memory element and allowing the use of new power supply and programming voltages. The present invention further provides a fabrication process for forming and producing a flash memory structure having a specially formed treatment layer formed as a protective layer disposed between a bottom oxide layer member of an ONO interpoly dielectric stack such that the characteristics of the subsequently formed ONO interpoly dielectric stack are optimized and improved, notwithstanding adverse thinning action caused by the dielectric stack fabrication process.
In particular, the flash memory structure of the present invention is formed via a fabrication process whereby, at a partially formed stage of a memory element, stacks of a first poly-crystalline silicon material or of an amorphous silicon (polysilicon) material, having an underlying thin film of silicon dioxide and a first (bottom) interpoly dielectric layer member formed overlying the first polysilicon material, are further processed to form a treatment layer, in accordance with the teachings of the present invention. The treatment layer will function as a protective layer for the bottom interpoly dielectric layer member and will be disposed between other interpoly dielectric layer members of a multi-layered interpoly dielectric stack, such as an ONO stack. The treatment layer can be termed post-treatment layer to distinguish from a pre-interpoly dielectric treatment layer taught in Applicants' co-pending related U.S. Provisional Patent Application, filed Aug. 13, 1999, Ser. No. 60/148,899, entitled “FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER AND METHOD OF FORMING,” referenced by Assignee's internal number D925, and hereby incorporated by reference. Instead of exposing the polysilicon stacks to a selected one of at least three ambient reagent gases (in accordance with known industry methods), the bottom interpoly dielectric layer member is first formed, and is then exposed to a selected one of at least three ambient reagent gases. The present invention distinguishes over the related art in that, rather than completing the interpoly dielectric stack, the bottom interpoly dielectric layer member is protected by the post-treatment layer of the present invention. The selected ambient reagent gases and exposure of the bottom interpoly dielectric layer member is performed in a fabrication tool such as a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. The at least three ambient reagent gases are grouped in an ambient reagent gases group consisting essentially of: (1) nitrous oxide (N
2
O) and/or nitric oxide (NO), (2) oxygen (O
2
) and/or water (H
2
O), and (3) ammonia (NH
3
). Any one ambient reagent gas may be selected and utilized in any of the foregoing fabrication tools for post-treating the surface of the bottom interpoly dielectric layer member prior to forming the other interpoly dielectric structure member of the flash memory element. Other features of the present invention are disclosed or are apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION.”
REFERENCES:
patent: 5940718 (1999-08-01), Ibok et al.
patent: 6235586 (2001-05-01), Au et al.
Halliyal Arvind
Ogle, Jr. Robert B.
Advanced Micro Devices , Inc.
Bowers Charles
Kilday Lisa
LaRiviere Grubman & Payne, LLP
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