Flash memory device with a variable erase pulse

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185190, C365S185290

Reexamination Certificate

active

06903974

ABSTRACT:
A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase pulse to the flash cell, and reading the flash cell. For each time the flash cell is read and is not in an erased state, the method includes applying a short erase pulse to the flash cell, counting the short erase pulse, and reading the flash cell. Finally, a length of the long erase pulse is adjusted based on the counted number of short erase pulses that were applied to the flash cell. The length of the long erase pulse may be increased if the counted number of short erase pulses is more than a high number of pulses, or it may be decreased if the counted number of short erase pulses is less than a low number of pulses. The length of the long erase pulse may be adjusted based on a past average of short erase pulses applied to the flash cell, or a quantity representing short erase pulses applied to the flash cell over a selected number of prior erases of the flash cell. The flash memory device may have a control circuit with elements to implement the method.

REFERENCES:
patent: 5636166 (1997-06-01), Roohparvar
patent: 5680350 (1997-10-01), Lee
patent: 5784316 (1998-07-01), Hirata
patent: 5801985 (1998-09-01), Roohparvar et al.
patent: 5901108 (1999-05-01), Roohparvar
patent: 5901194 (1999-05-01), Chevallier
patent: 5963480 (1999-10-01), Harari
patent: 6020775 (2000-02-01), Chevallier
patent: 6081575 (2000-06-01), Chevallier
patent: 6115291 (2000-09-01), Lakhani
patent: 6188613 (2001-02-01), Manning
patent: 6248629 (2001-06-01), Liu et al.
patent: 6272586 (2001-08-01), Roohparvar et al.
patent: 6356974 (2002-03-01), Chevallier

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