Synchronous global controller for enhanced pipelining

Details Synchronous global controller for enhanced pipelining Synchronous global controller for enhanced pipelining

2005-08-09

2005-08-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060

Reexamination Certificate

active

06928026

ABSTRACT:
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

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