Flash memory device with a novel redundancy selection...

Details Flash memory device with a novel redundancy selection... Flash memory device with a novel redundancy selection...

2000-06-02

2004-05-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C365S200000, C365S201000

Reexamination Certificate

active

06735727

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. 99-20445, filed on Jun. 3, 1999, and 99-22498, filed on Jun. 16, 1999, both with the Korean Industrial Property Office, which documents are hereby incorporated by reference.
FIELD OF THE INVENTION
This invention relates to semiconductor devices. More particularly, the invention relates to a redundancy selection circuit of a flash memory device and a method of using same that allows testing for defective redundant memory cells.
BACKGROUND OF THE INVENTION
Generally, semiconductor memory devices for storing data are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices lose their data at power-off, while the nonvolatile semiconductor memory devices maintain their data even at power-off. Therefore, the nonvolatile semiconductor memory devices have been widely used in applications in which power can be interrupted suddenly.
A nonvolatile semiconductor memory device, such as a flash memory device, comprises electrically erasable and programmable ROM cells, each of which is referred to as “a flash EEPROM cell”. The flash EEPROM cell includes a cell transistor. As illustrated in
FIG. 1
, the cell transistor has a semiconductor substrate (or bulk)
2
of a first conductive type (e.g., P-type), and source and drain regions
3
and
4
of a second conductive type (e.g., N-type) spaced from each other. A floating gate
5
for storing charges is placed over a channel region between the source and drain regions
3
and
4
, and a control gate
6
placed over the floating gate
5
. Gate
5
is understood to have a floating voltage potential. Other structure around it is not shown.
Programming of the flash EEPROM cell is carried out by a hot carrier injection mechanism. The hot carrier injection is performed by applying a high voltage (e.g., +10V) to its control gate
6
and an appropriate positive voltage (e.g., +5V-+6V) to its drain at the drain terminal V
d
. At this time, the bulk
2
of the EEPROM cell transistor is grounded, along with the source, by grounding the source terminal V
s
. According to this bias condition of the flash EEPROM cell, hot charge carriers are injected to the floating gate
5
from the channel region adjacent to the drain
4
, and thereby the threshold voltage of the EEPROM cell transistor is shifted into a target threshold voltage range for a programmed cell transistor (e.g., 6V-7V).
Erasing of the flash EEPROM cell is carried out by a Fowler-Nordheim (F-N) tunneling mechanism. The F-N tunneling is performed by applying a negative high voltage (e.g., −10V) to its control gate
6
and an appropriate positive voltage (e.g., +5V) to its bulk
2
. At this time, its source and drain remain at a high-impedance (or floating) state. According to this bias condition, negative electrons in the floating gate
5
are discharged into the source
3
or into the bulk
2
, and thereby the threshold voltage is shifted into a target threshold voltage range for an erased cell transistor (e.g., 1V-3V). The target threshold voltage distributions of the programmed and erased EEPROM cell transistors are illustrated in FIG.
2
.
Reading of the EEPROM cell transistor is carried out by applying a voltage of 4.5V to its gate
6
, and a voltage of 1V to its drain
4
. During reading, its source
3
and bulk
2
are grounded. According to this bias condition, the programmed EEPROM cell transistor conducts no current from its drain
4
to its source
3
, and is referred to as an “OFF” cell. On the other hand, the erased EEPROM cell transistor conducts current from its drain
4
to its source
3
, and is referred to as an “ON” cell.
The flash memory device includes an array of the flash EEPROM cells arranged along rows and columns, which are arranged orthogonally to each other. The density of defects generated in such a flash memory device during manufacturing is relatively independent of the integration density of the device, but is dependent on the semiconductor manufacturing technology. The higher the integration density of the device, the greater is the ratio of the number of normal memory cells to that of defective memory cells. Even if the device, however, includes only one defective memory cell therein, the device cannot operate normally, and therefore, the device is abandoned (discarded). This limits the manufacturing yield.
In order to be able to operate the flash memory device in spite of such defective memory cells, a redundant cell array is incorporated in the flash memory device along with the main cell array. In a flash memory device incorporating such a redundant cell array, the manufacturing yield can be improved.
Referring to
FIG. 3
, a conventional flash memory device includes a main cell array
10
with a plurality of first columns of main memory cells and a redundant cell array
20
with a plurality of second columns of redundant memory cells. Furthermore, the flash memory device includes a circuit
30
for replacing a first column of at least one defective memory cell (or a defective column of main memory cells) with a second column of redundant memory cells. Hereinafter, such a circuit
30
is named “a redundancy selection circuit”.
As illustrated in
FIG. 3
, an address storage block
32
and an input/output coding block
34
constitute the redundancy selection circuit
30
. The address storage block
32
stores column addresses for defective columns so that a defective column in the main cell array
10
can be replaced with a redundant column in the redundant cell array
20
by use of fuse elements (e.g., electrical fuses or laser beam fuses). The input/output coding block
34
generates redundancy selection signals RS
i
in response to output signals from the address storage block
32
. The redundancy selection signals RS
i
correspond to input/output pins I/O (in this embodiment, i=0-15) of the flash memory device, respectively.
During reading, a column pass gate circuit
40
responds to output signals from a column decoder circuit
50
and selects a part of first columns in the main cell array
10
and at least one of second columns in the redundant cell array
20
. The selected columns of the main cell array
10
correspond to the input/output pins I/O
0
-I/O
15
, respectively. Simultaneously, a row address decoder
60
decodes row addresses RA into signals WL
0
, . . . , WL
m
.
Then a sense amplifier SA and write driver WD circuit
70
reads out data from the main cell array
10
via the selected columns. A sense amplifier and write driver circuit
80
reads out data from the redundant cell array
20
via the selected column. If the column address CA inputted in block
32
equals a stored address in the address storage block
32
, one of the redundancy selection signals RS
i
is activated. This happens because one of the selected columns in the main cell array
10
is defective. Therefore, a multiplexer circuit
90
responds to the activated redundancy selection signal RS
i
, and selects data read out via the selected column of the redundant cell array
20
, instead of data read out via the defective column of the main cell array
10
. An I/O buffer
100
outputs the data from multiplexer
90
.
A problem arises when the address storage block
32
stores addresses for defective columns by cutting electrical or laser beam fuses incorporated in the blocks
32
and
34
at a wafer level or at a package level. This problem is that it is impossible to test all redundant memory cells in the redundant cell array
20
for defects. In order to solve this drawback, additional circuitry has been used for enabling the redundant memory cells to be estimated. However, the additional circuitry occupies space, which makes the size of the flash memory device increase. Furthermore, cutting the fuses of the redundancy selection circuit
30
takes a long time.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a flash memory devi

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