Flash memory device for performing bad block management and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S710000

Reexamination Certificate

active

07434122

ABSTRACT:
A flash memory device for performing a bad block management and a method of performing bad block management are implemented in hardware level. During a booting procedure of a flash memory device, a bad block-mapping table stored in a predetermined block of memory cell array unit or other nonvolatile memory is stored in a bad block mapping register via a bad block-mapping table loader. An address selector receives a logical address from an external device and compares the logical address with a bad block address stored in the bad block mapping register. A bad block-state controller determines a count number of a re-mapping mark and outputs a re-mapping mark flag to the address selector. The address selector selects a logical address or a bad block address received from the bad block mapping register as a physical address and outputs the physical address to the memory cell array unit.

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patent: 6016275 (2000-01-01), Han
patent: 6128695 (2000-10-01), Estakhri et al.
patent: 6288940 (2001-09-01), Kawamura
patent: 6684345 (2004-01-01), Harari et al.
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patent: 7-201196 (1995-08-01), None
patent: 1999-55972 (1999-07-01), None
patent: 2000-70451 (2000-11-01), None
English language abstract of Japanese Publication No. 7-201196.
English language abstract of Korean Publication No. 1999-55972.
English language abstract of Korean Publication No. 2000-70451.

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